ADV7174 Datasheet, PDF (28/52 Pages) Analog Devices – Chip Scale PAL/NTSC Video Encoder with Advanced Power Management

ADV7174/ADV7179
MODE REGISTER 0 (MR0)
Bits:
Address:
MR07 – MR00
SR4–SR0 = 00H
Figure 38 shows the various operations under the control of Mode Register 0. This register can be read from as well as written to.
MR07
MR06
MR05
MR04
MR03
MR02
MR01
MR00
CHROMA FILTER SELECT
MR07 MR06 MR05
0 0 0 1.3 MHz LOW-PASS FILTER
0 0 1 0.65 MHz LOW-PASS FILTER
0 1 0 1.0 MHz LOW-PASS FILTER
0 1 1 2.0 MHz LOW-PASS FILTER
1 0 0 RESERVED
1 0 1 CIF
1 1 0 QCIF
1 1 1 RESERVED
OUTPUT VIDEO
STANDARD SELECTION
MR01 MR00
0 0 NTSC
0 1 PAL (B, D, G, H, and I)
1 0 PAL (M)
1 1 RESERVED
LUMA FILTER SELECT
MR04 MR03 MR02
0 0 0 LOW-PASS FILTER (NTSC)
0 0 1 LOW-PASS FILTER (PAL)
0 1 0 NOTCH FILTER (NTSC)
0 0 1 NOTCH FILTER (PAL)
1 0 0 EXTENDED MODE
1 0 1 CIF
1 1 0 QCIF
1 1 1 RESERVED
Figure 38. Mode Register 0
Table 9. MR0 Bit Description
Bit Name
Bit No.
Output Video Standard
Selection
MR01–MR00
Luminance Filter Control MR02–MR04
Chrominance Filter Control MR05–MR07
Description
These bits are used to set up the ENCODE mode. The ADV7174/ADV7179 can be set up to
output NTSC, PAL (B/D/G/H/I), and PAL (M and N) standard video.
PAL M is available on the ADV7174 only.
These bits specify which luminance filter is to be selected. The filter selection is made
independent of whether PAL or NTSC is selected.
These bits select the chrominance filter. A low-pass filter can be selected with a choice of
cutoff frequencies 0.65 MHz, 1.0 MHz, 1.3 MHz, or 2 MHz, along with a choice of CIF or QCIF
filters.
Rev. A | Page 28 of 52