ADUC7122 Datasheet, PDF (28/92 Pages) Analog Devices – Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI® MCU

ADuC7122
ACQ
BIT TRIAL WRITE
ADC CLOCK
CONV_START
ADC_BUSY
ADCDAT
DATA
ADCSTA = 0
ADCSTA = 1
ADC INTERRUPT
Figure 16. ADC Timing
Preliminary Technical Data
TEMPERATURE SENSOR
The ADuC7122 provides a voltage output from an on-chip
band gap reference proportional to absolute temperature. This
voltage output can also be routed through the front-end ADC
multiplexer (effectively, an additional ADC channel input),
facilitating an internal temperature sensor channel that
measures die temperature.
The internal temperature sensor is not designed for use as an
absolute ambient temperature calculator. It is intended for use
as an approximate indicator of the temperature of the
ADuC7122 die.
The typical temperature coefficient is −0.707 mV/°C.
ADC MMRs Interface
The ADC is controlled and configured via a number of MMRs
(see Table 27) that are described in detail in the following pages.
ADC Output vs. Temperature
Table 27. ADC MMRs
Name Description
ADCCON ADC control register. Allows the programmer to enable the ADC peripheral, to select the mode of operation of the ADC (either
single-ended, pseudo differential, or fully differential mode), and to select the conversion type (see Table 28).
ADCCP ADC positive channel selection register.
ADCCN ADC negative channel selection register.
ADCSTA
ADC status register. Indicates when an ADC conversion result is ready. The ADCSTA register contains only one bit, ADCREADY
(Bit 0), representing the status of the ADC. This bit is set at the end of an ADC conversion generating an ADC interrupt. It is
cleared automatically by reading the ADCDAT MMR. When the ADC is performing a conversion, the status of the ADC can be
read externally via the ADCBusy pin. This pin is high during a conversion. When the conversion is finished, ADCBusy goes back low.
This information can be available on P0.5 (see the General-Purpose I/O section) if enabled in GP0CON register.
ADCDAT ADC data result register. Holds the 12-bit ADC result, as shown Table 30.
ADCRST ADC reset register. Resets all the ADC registers to their default value.
PGA_GN Gain of PADC0 and PADC1.
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