ADSP-2185NKSTZ-320 Datasheet, PDF (28/48 Pages) Analog Devices – DSP Microcomputer

ADSP-218xN
Clock Signals and Reset
Table 15. Clock Signals and Reset
Parameter
Min
Max
Unit
Timing Requirements:
t_CKI
CLKIN Period
t_CKIL
CLKIN Width Low
t_CKIH
CLKIN Width High
Switching Characteristics:
25
40
ns
8
ns
8
ns
t_CKL
CLKOUT Width Low
t_CKH
CLKOUT Width High
t_CKOH
CLKIN High to CLKOUT High
Control Signals Timing Requirements:
0.5t_CK – 3
ns
0.5t_CK – 3
ns
0
8
ns
t_RSP
RESET Width Low
t_MS
Mode Setup before RESET High
t_MH
Mode Hold after RESET High
5t_CK1
ns
7
ns
5
ns
1 _{Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles, assuming stable CLKIN (not including crystal oscillator}
start-up time).
CLKIN
CLKOUT
t_CKI
t_CKIH
t_CKIL
t_CKOH
t_CKH
t_CKL
MODE A D
RESET
t_MS
t_MH
t_RSP
Figure 26. Clock Signals and Reset
Rev. A | Page 28 of 48 | August 2006