ADSP-21477KCPZ-1A Datasheet, PDF (28/76 Pages) Analog Devices – SHARC Processor

ADSP-21477/ADSP-21478/ADSP-21479
Clock Input
Table 20. Clock Input
200 MHz
266 MHz
Parameter
Min
Max
Min
Max
Timing Requirements
t_CK
t_CKL
t_CKH
t_CKRF
t_CCLK2
f_VCO3
t_CKJ4, ⁵
CLKIN Period
CLKIN Width Low
CLKIN Width High
CLKIN Rise/Fall (0.4 V to 2.0 V)
CCLK Period
VCO Frequency
CLKIN Jitter Tolerance
40
20
20
5
200
–250
100
45
45
3
10
600
+250
30¹
15
15
3.75
200
–250
100
45
45
3
10
600
+250
1 _{Applies only for CLKCFG1–0 = 00 and default values for PLL control bits in PMCTL.}
2 _{Any changes to PLL control bits in the PMCTL register must meet core clock timing specification tcclk.}
3 _{See Figure 5 on Page 26 for VCO diagram.}
4 _{Actual input jitter should be combined with ac specifications for accurate timing analysis.}
5 _{Jitter specification is maximum peak-to-peak time interval error (TIE) jitter.}
CLKIN
t_CK
t_CKJ
t_CKH
t_CKL
Figure 7. Clock Input
300 MHz
Min
Max
26.66¹
13.33
13.33
3.33
200
–250
100
45
45
3
10
600
+250
Unit
ns
ns
ns
ns
ns
MHz
ps
Rev. C | Page 28 of 76 | July 2013