ADSP-21065LCSZ-240 Datasheet, PDF (28/44 Pages) Analog Devices – DSP Microcomputer

ADSP-21065L
DMA Handshake
These specifications describe the three DMA handshake modes. In all three modes DMAR is used to initiate transfers. For hand-
shake mode, DMAG controls the latching or enabling of data externally. For external handshake mode, the data transfer is controlled
by the ADDR_23-0, RD, WR, SW, MS_3-0, ACK, and DMAG signals. External mode cannot be used for transfers with SDRAM. For
Paced Master mode, the data transfer is controlled by ADDR_23-0, RD, WR, MS_3-0, and ACK (not DMAG). For Paced Master mode,
the Memory Read-Bus Master, Memory Write-Bus Master, and Synchronous Read/Write-Bus Master timing specifications for
ADDR_23-0, RD, WR, MS_3-0, SW, DATA_31-0, and ACK also apply.
Parameter
Min
Max
Unit
Timing Requirements:
t_SDRLC
t_SDRHC
t_WDR
t_SDATDGL
t_HDATIDG
t_DATDRH
t_DMARLL
t_DMARH
DMARx Low Setup Before CLKIN¹
DMARx High Setup Before CLKIN¹
DMARx Width Low (Nonsynchronous)
Data Setup After DMAGx Low²
Data Hold After DMAGx High
Data Valid After DMARx High²
DMARx Low Edge to Low Edge
DMARx Width High
5.0
5.0
6.0
0.0
18.0 + 14 DT
6.0
ns
ns
ns
15.0 + 20 DT
ns
ns
25.0 + 14 DT
ns
ns
ns
Switching Characteristics:
t_DDGL
DMAGx Low Delay After CLKIN
t_WDGH
DMAGx High Width
t_WDGL
t_HDGC
DMAGx Low Width
DMAGx High Delay After CLKIN
t_DADGH
Address Select Valid to DMAGx High
t_DDGHA
t_VDATDGH
Address Select Hold After DMAGx High
Data Valid Before DMAGx High³
t_DATRDGH
Data Disable After DMAGx High⁴
t_DGWRL
t_DGWRH
WR Low Before DMAGx Low
DMAGx Low Before WR High
t_DGWRR
t_DGRDL
WR High Before DMAGx High
RD Low Before DMAGx Low
t_DRDGH
t_DGRDR
RD Low Before DMAGx High
RD High Before DMAGx High
t_DGWR
DMAGx High to WR, RD Low
14.0 + 10 DT
10.0 + 12 DT + HI
16.0 + 20 DT
0.0 – 2 DT
28.0 + 16 DT
–1.0
16.0 + 20 DT
0.0
5.0 + 6 DT
18.0 + 19 DT + W
0.75 + 1 DT
5.0
24.0 + 26 DT + W
0.0
5.0 + 6 DT + HI
20.0 + 10 DT
ns
ns
ns
6.0 – 2 DT
ns
ns
ns
ns
4.0
ns
8.0 + 6 DT
ns
ns
3.0 + 1 DT
ns
8.0
ns
ns
2.0
ns
ns
W = (number of wait states specified in WAIT register) ¥ t_CK.
HI = t_CK (if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
NOTES
1_{Only required for recognition in the current cycle.}
2_{tSDATDGL is the data setup requirement if DMARx is not being used to hold off completion of a write. Otherwise, if DMARx low holds off completion of the write, the}
data can be driven t_DATDRH after DMARx is brought high.
3_{tVDATDGH is valid if DMARx is not being used to hold off completion of a read. If DMARx is used to prolong the read, then tVDATDGH = 8 + 9 DT + (n ¥ tCK) where n}
equals the number of extra cycles that the access is prolonged.
4_{See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.}
–28–
REV. C