AD9882_15 Datasheet, PDF (28/36 Pages) Analog Devices – Dual Interface for Flat Panel Displays

AD9882
11
5
GREEN Clamp Select
A bit that determines whether the GREEN channel is clamped
to ground or to midscale.
Table XXIV. GREEN Clamp Select Settings
Clamp
Function
0
Clamp to ground
1
Clamp to midscale (Pin 74)
The default setting for this register is 0.
11
4
BLUE Clamp Select
A bit that determines whether the BLUE channel is clamped to
ground or to midscale.
Table XXV. BLUE Clamp Select Settings
Clamp
Function
0
Clamp to ground
1
Clamp to midscale (Pin 74)
The default setting for this register is 0.
11 3 Coast Select
This bit is used to enable or disable the coast signal. If coast is
enabled, the additional decision of using the Vsync input pin or
the output from the sync separator needs to be made (Register
10H, Bits 1, 0). To disable coast, the user must set Register 11H,
Bit 2 to 1 and 11H, Bit 1 to 1.
Table XXVI. Coast Enable Settings
Select
Result
0
Coast disabled
1
Internally generated coast signal
The default for this register is 1.
11 2 Coast Input Polarity Override
This register is used to override the internal circuitry that deter-
mines the polarity of the coast signal going into the PLL. When
disabling coast, Register 11, Bit 2 must be set to 1 and Register
11H, Bit 1 must be set to 1. This register only works when Coast
is disabled. It does not work with internal Coast.
Table XXVII. Coast Input Polarity Override Settings
Override Bit Result
0
Coast polarity determined by chip
1
Coast polarity determined by user
The default for coast polarity override is 0.
11 1 Coast Input Polarity
A bit to indicate the polarity of the coast signal that is applied to
the PLL coast input.
This register can only be used when coast is disabled and
Register 11H, Bit 2 is set to 1.
12 7–0 Pre-Coast
This register allows the coast signal to be applied prior to the
Vsync signal. This is necessary in cases where pre-equalization
pulses are present. This register defines the number of edges
that will be filtered before Vsync on a composite sync.
The default is 0.
13 7–0 Post-Coast
This register allows the coast signal to be applied following the
Vsync signal. This is necessary in cases where post-equalization
pulses are present. The step size for this control is one Hsync
period. This register defines the number of edges that will be
filtered after Vsync on a composite sync.
The default is 0.
14 7–6 Output Drive
The two bits select the drive strength for the high speed digital
outputs (all data output and clock output pins). Higher drive
strength results in faster rise/fall times, and in general makes it
easier to capture data. Lower drive strength results in slower
rise/fall times and helps reduce EMI and digitally generated
power supply noise.
Table XXIX. Output Drive Strength Settings
Bit 7
Bit 6
Result
1
X
High drive strength
0
1
Medium drive strength
0
0
Low drive strength
The default for this register is 11, high drive strength. (This option works on
both the analog and digital interfaces.)
14 5 Programmable Analog Bandwidth
Bits that select the analog bandwidth.
Bit 5
0
1
Table XXX. Analog Bandwidth Control
Analog Bandwidth
10 MHz
300 MHz
14 4 Clk Inv
Data Output Clock Invert
A control bit for the inversion of the output data clock (Pin 85).
This function works only for the digital interface. When not
inverted, data is output on the falling edge of the data clock.
See the timing diagrams, Figures 14 and 15, to see how this
affects timing.
Table XXXI. Clock Output Invert Settings
Clk Inv
Function
0
Not inverted
1
Inverted
The default for this register is 0 (not inverted).
Table XXVIII. Coast Input Polarity Settings
CSTPOL Function
0
Active LOW
1
Active HIGH
The power-up default value is CSTPOL = 1.
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