AD9779A_15 Datasheet, PDF(28/56 Page) Analog Devices – Dual, 12-/14-/16-Bit,1 GSPS Digital-to-Analog Converters

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AD9779A_15 Datasheet, PDF (28/56 Pages) Analog Devices – Dual, 12-/14-/16-Bit,1 GSPS Digital-to-Analog Converters

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AD9776A/AD9778A/AD9779A

3-WIRE INTERFACE REGISTER MAP

Note that all unused register bits should be kept at the device default values.

Table 13.

Name

Comm

Digital

Control

Sync

Control

PLL

Control

Misc.

Control

I DAC

Control

Aux

DAC1

Control

Q DAC

Control

Aux

DAC2

Control

Interrupt

Version

Address

Hex Decimal

0x00 00

0x01 01

0x02 02

0x03 03

0x04 04

0x05 05

0x06 06

0x07 07

0x08 08

0x09 09

0x0A 10

0x0B 11

0x0C 12

0x0D 13

0x0E 14

0x0F 15

0x10 16

0x11 17

0x12 18

0x13

0x18

0x19

19 to 24

0x1F 31

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

SDIO

LSB/MSB

bidirectional first

Software

reset

Power-

down

mode

Auto

power-

down

enable

PLL lock

indicator

(read

only)

Interpolation Factor[1:0]

Filter Modulation Mode[3:0]

DATACLK

Delay[4]

Zero

stuffing

enable

Data format Single port

Real mode

DATACLK

delay

enable

Inverse

sinc

enable

DATACLK TxEnable

invert

Q first

DATACLK Reserved

delay mode (set to 1)

DATACLK Divide[1:0]

Data Timing Margin[3:0]

DATACLK Delay[3:0]

SYNC_O Divide[2:0]

SYNC_O

Delay[4]

SYNC_O Delay[3:0]

SYNC_I Ratio[2:0]

SYNC_I

Delay[4]

SYNC_I Delay[3:0]

SYNC_I Timing Margin[3:0]

SYNC_I

enable

SYNC_O

enable

SYNC_O

triggering

edge

Clock State[4:0]

PLL Band Select[5:0]

PLL VCO Drive[1:0]

PLL enable PLL VCO Divide Ratio[1:0]

PLL Loop Divide

Ratio[1:0]

PLL Bias[2:0]

VCO Control Voltage[2:0] (read only)

PLL Loop Bandwidth[4:0]

I DAC sleep

I DAC

power-

down

Auxiliary

DAC1 sign

Auxiliary

DAC1

current

direction

Q DAC sleep Q DAC

power-

down

Auxiliary

DAC2 sign

Auxiliary

DAC2

current

direction

I DAC Gain Adjustment[7:0]

Auxiliary DAC1 Data[7:0]

Auxiliary

DAC1

power-

down

Q DAC Gain Adjustment[7:0]

Auxiliary DAC2 Data[7:0]

Auxiliary

DAC2

power-

down

Reserved

I DAC Gain

Adjustment[9:8]

Auxiliary DAC1

Data[9:8]

Q DAC Gain

Adjustment[9:8]

Auxiliary DAC2

Data[9:8]

Data timing Sync timing

error IRQ

Data

timing

error type

Data

timing

error

IRQ

enable

Version[7:0]

Sync

timing

error IRQ

enable

Internal

sync

loopback

Def.

0x00

0xE7

0x52

0x1F

0xF9

0x01

0x00

0xF9

0x01

0x00

0x07

Rev. B | Page 28 of 56

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