AD9652 Datasheet, PDF (28/36 Pages) Analog Devices – 16-Bit, 310 MSPS, 3.3 V/1.8 V Dual Analog-to-Digital Converter (ADC)

AD9652
FAST THRESHOLD DETECTION (FDA/FDB)
In receiver applications, it is desirable to have a mechanism to
reliably determine when the converter is about to be clipped.
The standard overflow indicator on the OR± pins provide
delayed information, which is synchronized with the output
data. The delayed indicator is of limited value in preventing
clipping in this case. Therefore, it is helpful to have a programmable
threshold below full scale that allows time to reduce external
gain before the clip occurs. In addition, because input signals
can have significant slew rates, latency of this function is of
concern.
Using the SPI port, the user can provide a threshold above
which the fast detect (FD) output is active. Bit 0 of Register 0x45
enables the FD feature. Register 0x47 to Register 0x4C allow the
user to set the threshold levels and timing. As long as the signal
is below the selected threshold, the FD output remains low. In
this mode, the magnitude of the data is considered in the calcu-
lation of the condition, but the sign of the data (either positive
or negative) is not considered. The threshold detection responds
identically to positive and negative signals outside the desired
range (magnitude).
The fast detect indicators, FDA for Channel A and FDB for
Channel B, are asserted when the input magnitude exceeds the
value programmed in the fast detect upper threshold register,
Register 0x47. The selected threshold register is compared with
Data Sheet
the signal magnitude at the output of the ADC. The fast upper
threshold detection has a latency of seven clock cycles. The
approximate upper threshold is a 4-bit value defined by
Upper Threshold (% Full Scale) =
((Register 0x47 value)/8) × 100%
The FD indicators are not cleared until the signal drops below
the lower threshold for the programmed dwell time. The lower
threshold is programmed in the fast detect lower threshold
registers, Register 0x49 and Register 0x4A. The fast detect lower
threshold register is a 15-bit register that is compared with the
signal magnitude at the output of the ADC. This comparison is
subject to the ADC pipeline latency but is accurate in terms of
converter resolution. The lower threshold is defined by
Lower Threshold (% Full Scale) =
((Register 0x49/Register 0x4A value)/32767) × 100%
For example, to set an upper threshold of 50% full scale, write
0x04 to Register 0x47, and to set a lower threshold of 40% full
scale, write 0x3333 to Register 0x49 and Register 0x4A.
The dwell time can be programmed from 1 sample clock cycle
to 65,535 sample clock cycles by placing the desired value in the
fast detect dwell time registers, Register 0x4B and Register 0x4C
(see Figure 66).
UPPER THRESHOLD
FDA OR FDB
DWELL TIME
TIMER RESET BY
RISE ABOVE
LOWER
THRESHOLD
LOWER THRESHOLD
DWELL TIME
Figure 66. Threshold Settings for FDA and FDB Signals
TIMER COMPLETES BEFORE
SIGNAL RISES ABOVE
LOWER THRESHOLD
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