AD5424_1 Datasheet, PDF (28/32 Pages) Analog Devices – 8-/10-/12-Bit, High Bandwidth Multiplying DACs with Parallel Interface

AD5424/AD5433/AD5445
OUTLINE DIMENSIONS
5.10
5.00
4.90
16
9
4.50
4.40
4.30
1
6.40
BSC
8
PIN 1
1.20
0.15
MAX
0.20
0.05
0.09
0.75
0.30
8°
0.60
0.65
BSC
0.19 SEATING
PLANE
0°
0.45
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 63. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
6.60
6.50
6.40
20
11
4.50
4.40
4.30
6.40 BSC
1
10
PIN 1
0.65
BSC
0.15
1.20 MAX
0.20
0.05
0.09
0.75
0.30
COPLANARITY 0.19
8°
SEATING
0°
0.60
0.45
0.10
PLANE
COMPLIANT TO JEDEC STANDARDS MO-153-AC
Figure 64. 20-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-20)
Dimensions shown in millimeters
4.00
BSC SQ
PIN 1
INDICATOR
TOP VIEW
1.00 ^{12° MAX}
0.85
0.80
SEATING
PLANE
0.80 MAX
0.65 TYP
0.30
0.23
0.18
0.60 MAX
0.60 MAX
3.75
BCS SQ
0.50
BSC
0.75
0.60
0.50
15 ₁₆
20
1
EXPOSED
PAD
(BOTTOM VIEW)
10
11
5
6
PIN 1
INDICATOR
2.25
2.10 SQ
1.95
0.25 MIN
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-1
Figure 65. 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm × 4 mm Body, Very Thin Quad
(CP-20-1)
Dimensions shown in millimeters
Rev. B | Page 28 of 32