ADSP-BF522C_15 Datasheet, PDF (27/36 Pages) Analog Devices – Blackfin Embedded Processor with Codec

ADSP-BF522C/ADSP-BF523C/ADSP-BF524C/ADSP-BF525C/ADSP-BF526C/ADSP-BF527C
Digital Audio Interface Slave Mode Timing
Table 19. Digital Audio Interface Slave Mode Timing
Parameter
Test Conditions¹ Min Max Unit
t_DS
DACDAT setup time from CODEC_BCLK rising edge
10
ns
t_DH
DACDAT hold time from CODEC_BCLK rising edge
t_LRSU
ADCLRC/DACLRC setup time to CODEC_BCLK rising edge
t_LRH
ADCLRC/DACLRC hold time to CODEC_BCLK rising edge
t_DD
ADCDAT propagation delay from CODEC_BCLK falling edge (external load of 70 pF)
t_BCH
CODEC_BCLK pulse width high
t_BCL
CODEC_BCLK pulse width low
t_BCY
CODEC_BCLK cycle time
10
ns
10
ns
10
ns
30 ns
25
ns
25
ns
50
ns
1 _{AVDD, HPVDD, VDDEXT = 3.3 V, AGND = 0 V, TA = +25°C, Slave Mode, fS = 48 kHz, XTI/CODEC_MCLK = 256 × fS unless otherwise stated.}
CODEC_BCLK
tBCH
tBCL
tBCY
DACLRC/
ADCLRC
DACDAT
ADCDAT
tDS
tLRH
tLRSU
tDD
tDH
Figure 20. Digital Audio Interface Slave Mode Timing
Rev. A | Page 27 of 36 | March 2010