ADAU1452 Datasheet, PDF (27/180 Pages) Analog Devices – SigmaDSP Digital Audio Processor

Data Sheet
ADAU1452/ADAU1451/ADAU1450
MASTER CLOCK, PLL, AND CLOCK GENERATORS
Clocking Overview
To externally supply the master clock, connect the clock source
directly to the XTALIN/MCLK pin. Alternatively, use the
internal clock oscillator to drive an external crystal.
Using the Oscillator
The ADAU1452/ADAU1451/ADAU1450 can use an on-board
oscillator to generate its master clock. However, to complete the
oscillator circuit, an external crystal must be attached. The on-
board oscillator is designed to work with a crystal that is tuned
to resonate at a frequency of the nominal system clock divided
by 24. For a normal system, where the nominal system clock is
294.912 MHz, this frequency is 12.288 MHz.
The fundamental frequency of the crystal can be up to 30 MHz.
Practically speaking, in most systems the fundamental frequency of
the crystal should be in a range from 3.072 MHz to 24.576 MHz.
For the external crystal in the circuit, use an AT-cut parallel
resonance device operating at its fundamental frequency. Do not
use ceramic resonators, because of their poor jitter performance.
Quartz crystals are ideal for audio applications. Figure 15 shows
the crystal oscillator circuit that is recommended for proper
operation.
XTALIN/MCLK
22pF
XTALOUT
100Ω
12.288MHz
22pF
Figure 15. Crystal Resonator Circuit
Do not use XTALOUT to directly drive the crystal signal to
another IC. This signal is an analog sine wave with low drive
capability and, therefore, is not appropriate to drive an external
digital input. A separate pin, CLKOUT, is provided for this pur-
pose. The CLKOUT pin is set up using the MCLK_OUT register
(Address 0xF005). For a more detailed explanation of CLKOUT,
refer to the Master Clock Output section or the register map
description of the MCLK_OUT register (see the CLKOUT
Control Register section).
If a clock signal is provided from elsewhere in the system directly
to the XTALIN/MCLK pin, the crystal resonator circuit is not
necessary, and the XTALOUT pin can remain disconnected.
Setting the Master Clock and PLL Mode
An integer PLL is available to generate the core system clock
from the master clock input signal. The PLL generates the nominal
294.912 MHz core system clock to run the DSP core. As a result of
the flexible clock generator circuitry, this nominal core clock
frequency can be used for a variety of audio sample rates. An
integer prescaler takes the clock signal from the MCLK pin and
divides its frequency by 1, 2, 4, or 8 to meet the appropriate
frequency range requirements for the PLL itself. The nominal
input frequency to the PLL is 3.072 MHz. For systems with
an 11.2896 MHz input master clock, the input to the PLL is
2.8224 MHz.
XTALIN/
MCLK
1, 2, 4, (DEFAULT)
OR 8
96
÷
×
294.912MHz
SYSTEM CLOCK
NOMINALLY
3.072MHz
Figure 16. PLL Functional Block Diagram
The 100 Ω damping resistor on XTALOUT provides the oscillator
with a voltage swing of approximately 3.1 V at the XTALIN/
MCLK pin. The optimal crystal shunt capacitance is 7 pF. Its
optimal load capacitance, specified by the manufacturer, should be
about 20 pF, although the circuit supports values of up to 25 pF.
Ensure that the equivalent series resistance is as small as possible.
Calculate the necessary values of the two load capacitors in the
circuit from the crystal load capacitance, using the following
equation:
C_L
=
C1× C2
C1 + C2
+ C_STRAY
where:
C1 and C2 are the load capacitors.
CSTRAY is the stray capacitance in the circuit. CSTRAY is usually
assumed to be approximately 2 pF to 5 pF, but it varies
depending on the PCB design.
Short trace lengths in the oscillator circuit decrease stray capaci-
tance, thereby increasing the loop gain of the circuit and helping
to avoid crystal start-up problems. Therefore, place the crystal
as near to the XTALOUT pin as possible, and on the same side
of the PCB.
The master clock input signal ranges in frequency from 2.375 MHz
to 36 MHz. For systems that are intended to operate at a 48 kHz,
96 kHz, or 192 kHz audio sample rate, the typical master clock
input frequencies are 3.072 MHz, 6.144 MHz, 12.288 MHz, and
24.576 MHz. Note that the flexibility of the PLL allows for a large
range of other clock frequencies, as well.
The PLL in the ADAU1452 and ADAU1451 has a nominal (and
maximum) output frequency of 294.912 MHz. The PLL of the
ADAU1450 outputs a frequency at half the rate of the PLL of the
ADAU1452 and ADAU1451, with a nominal (and maximum)
output frequency of 147.456 MHz.
The PLL is configured by setting Register 0xF000 (PLL_CTRL0),
Register 0xF001 (PLL_CTRL1), and Register 0xF002 (PLL_CLK_
SRC). After these registers are modified, set Register 0xF003, Bit 0
(PLL_ENABLE), forcing the PLL to reset itself and attempt to
relock to the incoming clock signal. Typically, the PLL locks
within 3.5 ms. When the PLL locks to an input clock and creates
a stable output clock, a lock flag is set in Register 0xF004, Bit 0
(PLL_LOCK).
On the EVAL-ADAU1452MINIZ evaluation board, the C1 and
C2 load capacitors are 22 pF.
Rev. C | Page 27 of 180