AD9959_08 Datasheet, PDF (27/44 Pages) Analog Devices – 4-Channel, 500 MSPS DDS with 10-Bit DACs

f_OUT
FTW1
B
B
AD9959
B
A
A
A
FTW0
SINGLE-TONE
MODE
P0 = 0
f_OUT
FTW1
P0 = 1
P0 = 0
P0 = 1
P0 = 0
LINEAR SWEEP MODE ENABLE—NO-DWELL BIT SET
Figure 38. Linear Sweep Mode (No-Dwell Enabled)
P0 = 1
B
TIME
A
FTW0
SINGLE-TONE
MODE
P0 = 0
LINEAR SWEEP MODE
P0 = 1
P0 = 0
TIME
AT POINT A: LOAD RISING RAMP RATE REGISTER, APPLY RDW<31:0>
AT POINT B: LOAD FALLING RAMP RATE REGISTER, APPLY FDW<31:0>
Figure 39. Linear Sweep Mode (No-Dwell Disabled)
SWEEP AND PHASE ACCUMULATOR CLEARING
FUNCTIONS
The AD9959 allows two different clearing functions. The first
is a continuous zeroing of the sweep logic and phase accumula-
tor (clear and hold). The second is a clear and release or automatic
zeroing function. CFR[4] is the autoclear sweep accumulator bit
and CFR[2] is the autoclear phase accumulator bit. The continuous
clear bits are located in CFR, where CFR[3] clears the sweep
accumulator and CFR[1] clears the phase accumulator.
Continuous Clear Bits
The continuous clear bits are static control signals that, when
active high, hold the respective accumulator at 0 while the bit is
active. When the bit goes low, the respective accumulator is
allowed to operate.
Clear and Release Bits
The autoclear sweep accumulator bit, when set, clears and
releases the sweep accumulator upon an I/O update or a change
in the profile input pins. The autoclear phase accumulator bit,
when set, clears and releases the phase accumulator upon an
I/O update or a change in the profile pins. The automatic
clearing function is repeated for every subsequent I/O update or
change in profile pins until the clear and release bits are reset
via the serial port.
Rev. B | Page 27 of 44