AD9862BSTZ Datasheet, PDF (27/32 Pages) Analog Devices – Mixed-Signal Front-End (MxFE™) Processor for Broadband Communications

AD9860/AD9862
Tx Path (Normal Operation)
The DAC update rate, the Tx input data rate, and the rate of
CLKOUT2 (clock used to latch Tx input data) are the parameters
of interest for the transmit path data. These parameters, in addition
to the output signal bandwidth, are related to CLKIN by the settings
of the ADC Div2, the DLL multiplier, the CLKOUT2 Div, the
two edges, and the interpolation registers.
The Tx data is timed relative to the CLKOUT2 pin (unless it is
retimed relative to CLKOUT1 by setting Tx Retime register) and
the input Tx data is latched on either each rising edge, each
falling edge or both edges (controlled through the Inverse Sample
and two edges registers). The timing diagrams for these cases
are shown in Figure 12.
The Dual Tx data is multiplexed onto a single bus so that fewer
digital bits are necessary to transfer data. Throughout this discus-
sion of Tx path timing, Tx digital processing options other than
interpolation are ignored because they do not change data timing;
Tx data timing reflects whether single or dual channel data is
latched into the AD9860/AD9862.
The rates of CLKOUT2 (and the input data rate) are related
to CLKIN by the DLL Multiplier Register, the setting of the
CLKOUT2 Divide Factor Register and the register ADC Div2.
These relationships are shown in Table II.
Table II. CLKOUT2 Timing Relative to CLKIN
for Normal Operation Mode
CLK DIV2
DLL
Mult
1Ï«
No Div
2Ï«
4Ï«
1Ï«
Div by 2
2Ï«
4Ï«
CLKOUT2
Div Factor
ր1
ր2
ր4
ր1
ր2
ր4
ր1
ր2
ր4
ր1
ր2
ր4
ր1
ր2
ր4
ր1
ր2
ր4
CLKOUT2
CLKIN
CLKIN/2
CLKIN/4
2Ï«CLKIN
CLKIN
CLKIN/2
4Ï«CLKIN
2Ï«CLKIN
CLKIN
CLKIN/2
CLKIN/4
CLKIN/8
CLKIN
CLKIN/2
CLKIN/4
2Ï«CLKIN
CLKIN
CLKIN/2
1؋, 1/2؋
DIV
1؋, 2؋, 4؋
CLKIN
DLL
ADC DIV2:
REG D24 B5
1؋, 1/2؋
DIV
CLKSEL
DLL MULTIPLIER:
REG D24 B3, 4
ADC
NO DECIMATION, 2
DECIMATE:
REG D6 B0
DATA MUX
AND
LATCH
MUX OUT: REG D5 B0
Rx RETIME: REG D5 B3
Rx DATA
[0:23]
1؋, 1/2؋, 1/4؋
DIV
NO INVERSION, INVERT
INV
CLKOUT1
INV1: REG D25 B1
NO INVERSION, INVERT
INV
CLKOUT2
CLKOUT2 DIV FACTOR:
REG 25 B6, 7
INV2: REG D25 B5
DAC
NO INTERP, 2, 4
DATA LATCH
AND
DEMUX
CLOCK PATH
DATA PATH
INTERPOLATION:
REG D19 B0, 1
2 DATA PATHS: REG D19 B4
Q/I ORDER: REG D18 B5
Tx RETIME: REG D18 B6
Figure 13. Alternative Operation Timing Block Diagram
Tx DATA
[0:13]
REV. 0
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