AD9229_15 Datasheet, PDF (27/40 Pages) Analog Devices – Quad, 12-Bit, 50/65 MSPS, Serial, LVDS, 3 V A/D Converter

AD9229
GND
AVDD_DUT ^{DIGITAL TEST}
PATTERN
ENABLE
DRVDD_DUT
R201
10kΩ
R202
10kΩ
2
1
3
JP202
PIN 1 TO PIN 2 = 1010 1010 1010
PIN 2 TO PIN 3 = 1000 0000 0000
PWDN ENABLE
JP201
AVDD_DUT
GND
R228
10kΩ
AVDD_DUT
R203
10kΩ
AVDD_DUT
GND
OPTIONAL CLOCK OSCILLATOR
VIN_A
VIN_A
GND
U201
1 _DRGND
2 _DRVDD
3 _DNC
4 _DTP
5 _AVDD
6 _AGND
7 _PDWN
8 _AVDD
9 _AGND
10 _{VIN +A}
11 _{VIN –A}
12 _AGND
AD9229
36
DRGND
35
DRVDD
34
LVDSBIAS
33
AGND
32
AVDD
31
AGND
30
CLK
29
AVDD
28
AGND
27
VIN +D
26
VIN –D
25
AGND
GND
DRVDD_DUT
GND
AVDD_DUT
R204
4.0kΩ
GND
DUTCLK
GND
AVDD_DUT
GND
VIN_D
VIN_D
GND
AVDD_VGA
AVDD_DUT
JP204
JP203
C209
0.1μF
OSC200
1
EOH
4
VCC
2
GND
3
OUTPUT
CBELV3I66MT
C210
0.1μF
OSC201
1
NC/ENB
14
VCC
7
GND
8
OUTPUT
CX3600C-65
DNP
AVDD_DUT
R225
0Ω
DNP
REFERENCE
DECOUPLING
DCO
C204
0.1μF
C203
0.1μF
C202
10μF
FCO
CHA
C201
0.1μF _CHB
CHC
CLOCK CIRCUIT
CHD
P201
ENCODE
INPUT
R213
49.9Ω
R212
1kΩ
R229
0Ω
C205 R211 R231
0.1μF 1kΩ 0Ω
DNP
U202
1
2
U202
3
4
R214
22Ω
AVDD_DUT:14 AVDD_DUT:14
GND:7
GND:7
DUTCLK
R230
0Ω
DNP
EXTERNAL REFERENCE CIRCUIT
AVDD_DUT
U203
ADR510/ADR520
TRIM/NC 1NV VOUT
R215
2kΩ
C206
0.1μF
R217
470kΩ
R216
10kΩ
REFERENCE CIRCUIT
R218
0Ω
DNP
VREF_DUT
VREF SELECT VREF = 1V = DEFAULT
R221
0Ω
VREF = 0.5V
C207
0.1μF
CW
C208
10μF
AVDD_DUT
R219
DNP
R220
DNP
R222
0Ω
R223
0Ω
R224
0Ω
VREF = EXTERNAL
VREF = 0.5V (1 + R219/R220)
VREF = 1V
VSENSE_DUT
REMOVE C208 WHEN
USING EXTERNAL VREF
DIGITAL OUTPUTS
P202
60
C10
40
59
C9
39
58
C8
38
57
C7
37
56
C6
36
55
C5
35
54
C4
34
53
C3
33
52
C2
32
51
C1
31
30
A10
10
29
A9
9
28
A8
8
27
A7
7
26
A6
6
25
A5
5
24
A4
4
23
A3
3
22
A2
2
21
A1
1
GNDCD10
R205
DNP
GNDCD9
R206
DNP
GNDCD8
R207
DNP
GNDCD7
R208
DNP
GNDCD6
R209
DNP
GNDCD5
R210
DNP
GNDCD4
GNDCD3
GNDCD2
GNDCD1
GNDAB10
GNDAB9
GNDAB8
GNDAB7
GNDAB6
GNDAB5
GNDAB4
GNDAB3
GNDAB2
GNDAB1
D10
50
D9
49
D8
48
D7
47
D6
46
D5
45
D4
44
D3
43
D2
42
D1
41
B10
20
B9
19
B8
18
B7
17
B6
16
B5
15
B4
14
B3
13
B2
12
B1
11
1469169-1
DNP : DO NOT POPULATE
R205-R210
OPTIONAL OUTPUT
TERMINATIONS
Figure 49. Evaluation Board Schematic, DUT, VREF, Clock Inputs, and Digital Output Interface
DCO
FCO
CHA
CHB
CHC
CHD
Rev. B | Page 27 of 40