AD7994 Datasheet, PDF (27/27 Pages) Analog Devices – 4-Channel, 12-/10-Bit ADCs with I2C Compatible Interface in 16-Lead TSSOP

PRELIMINARY TECHNICAL DATA
AD7994/AD7993
It is recommended that no I²C Bus activity occurs when a
conversion is taking place. However if this is not possible,
e.g. when operating in Mode 2 or Mode 3, then in order
to maintain the performance of the ADC, Bits D7 and D6
in the Cycle Timer Register are used to delay critical
sample intervals and bit trials from occurring while there
is activity on the I²C Bus. This will result in a quiet pe-
riod for each bit decision. In certain cases where there is
excessive activity on the interface lines this may have the
effect of increasing the overall Conversion time. However
if bit trial delays extend longer than 1 µs the conversion
will terminate.
When bits D7 and D6 are both 0, the bit trial and sample
interval delaying mechanism will be implemented. The
default setting of D7 and D6 is 0. To turn off both set D7
and D6 to 1.
Cycle Timer Register
D7
D6
D5 D4 D3 D2 D1 D0
Sample Bit Trial 0 0 0 Cyc Cyc Cyc
Dealy Delay
Bit2 Bit1 Bit0
0*
0*
0* 0* 0* 0* 0* 0*
*Default settings at Power-up
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Lead TSSOP (RU-16)
0.201 (5.10)
0.193 (4.90)
16
9
1
8
PIN
1
0.006 (0.15)
0.002 (0.05)
SEATING
PLANE
0.0256
(0.65)
BSC
0.0118 (0.30)
0.0075 (0.19)
0.0433
(1.10)
MAX
8°
0°
0.0079 (0.20)
0.0035 (0.090)
0.028 (0.70)
0.020 (0.50)
REV. PrF
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