ADSP-21991_15 Datasheet, PDF (26/44 Pages) Analog Devices – Mixed Signal DSP Controller

ADSP-21991
External Port Write Cycle Timing
Table 8 and Figure 9 describe external port write operations.
The external port lets systems extend read/write accesses in three
ways: wait states, ACK input, and combined wait states and
ACK. To add waits with ACK, the DSP must see ACK low at
the rising edge of EMI clock. ACK low causes the DSP to wait,
and the DSP requires two EMI clock cycles after ACK goes high
to finish the access. For more information, see the External Port
chapter in the ADSP-2199x DSP Hardware Reference.
Table 8. External Port Write Cycle Timing
Parameter^{1, 2}
Timing Requirements
t_AKW
t_DWSAK
ACK Strobe Pulsewidth
ACK Delay from XMS Low
Min
12.5
Max
0.5t_EMICLK – 1
Unit
ns
ns
Switching Characteristics
t_CSWS
t_AWS
t_WSCS
t_WSA
t_WW
t_CDA
t_CDD
t_DSW
t_DHW
t_DHW
t_WWR
Chip Select Asserted to WR Asserted Delay
0.5t_EMICLK – 4
ns
Address Valid to WR Setup and Delay
0.5t_EMICLK – 3
ns
WR Deasserted to Chip Select Deasserted
0.5t_EMICLK – 4
ns
WR Deasserted to Address Invalid
0.5t_EMICLK – 3
ns
WR Strobe Pulsewidth
t_EMICLK– 2 + W³
ns
WR to Data Enable Access Delay
0
ns
WR to Data Disable Access Delay
0.5t_EMICLK – 3
0.5t_EMICLK + 4
ns
Data Valid to WR Deasserted Setup
t_EMICLK+ 1 +W³
t_EMICLK + 7 + W³
ns
WR Deasserted to Data Invalid Hold Time; E_WHC^{4, 5} 3.4
ns
WR Deasserted to Data Invalid Hold Time; E_WHC^{4, 6} t_EMICLK+3.4
ns
WR Deasserted to WR, RD Asserted
t_HCLK
ns
1 _{tEMICLK is the External Memory Interface clock period. tHCLK is the peripheral clock period.}
2 _{These are timing parameters that are based on worst-case operating conditions.}
3 _{W = (number of wait states specified in wait register) ؋ tEMICLK.}
4 _{Write hold cycle–memory select control registers (MS ؋ CTL).}
5 _{Write wait state count (E_WWC) = 0}
6 _{Write wait state count (E_WWC) = 1}
MS3–0
IOMS
BMS
A21–0
WR
ACK
D15–0
RD
t_CSWS
t_AWS
t_WW
t_AKW
t_CDA
t_DWSAK
t_DSW
t_WSCS
t_WSA
t_WWR
t_CDD
t_DHW
Figure 9. External Port Write Cycle Timing
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