AD9784 Datasheet, PDF (26/52 Pages) Analog Devices – 14-Bit, 200 MSPS/500 MSPS TxDAC+ with 2×/4×/8× Interpolation and Signal Processing

AD9784
Preliminary Technical Data
DATAADJUST Synchronization
When designing the digital interface for high speed DACs, care
must be taken to ensure that the DAC input data meets setup-
and-hold requirements. Often, compensation must be used in
the clock delay path to the digital engine driving the DAC. The
AD9784 has the on chip capability to vary the DACCLK’s
latching edge. With the interpolation function enabled, this
allows the user the choice of multiple edges upon which to latch
the data. For instance, if the AD9784 is using 8× interpolation,
the user may latch from one of eight edges before the rising
edge of DATACLK, or seven edges after this rising edge. The
specific edge upon which data is latched is controlled by SPI
Register 05h, Bits 7:4. Table 26 shows the relationship of the
latching edge of DACCLK and DATACLK with the various
settings of the DATAADJ bits.
Figure 42, Figure 43, and Figure 44 show the alignment for the
latching edge of DACCLK with 4× interpolation and different
settings for DATAADJ. In Figure 42, DATAADJ is set to 0000,
with DCLKPOL set to 0 so that the latching edge of DACCLK is
immediately before the rising edge of DATACLK. The data
transitions shown in Figure 42 are synchronous with the
DACCLK, so that DACCLK and data are constant with respect
to each other. The only visible change when DATAADJ is
altered is that DATACLK moves, indicating the latching edge
has moved as well. Note that when DATAADJ is altered, the
latching edge with respect to DATACLK remains the same, but
the latching edge of DACCLK follows the edge of DATACLK.
RISING EDGE OF DATACLK
CONCURRENT WITH
LATCHING EDGE OF DACCLK
Table 26.
SPI Reg 05h
Bit 7 Bit 6 Bit 5
0
0
0
0
0
0
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
1
1
1
Bit 4
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Latching Edge wrt DATACLK
0
+1
+2
+3
+4
+5
+6
+7
–8
–7
–6
–5
–4
–3
–2
–1
Note that the data in Figure 40 and Figure 41 was taken with the
DATAADJ default of 0000. With DCLKPOL = 0, the latching
edge of DACCLK is just previous to the rising edge of
DATACLK; with DCLKPOL = 1, the latching edge of DACCLK
is just previous to the falling edge of DATACLK.
With 8× interpolation, the user has the capability of using one
of 16 edges to latch the data. This is due to the fact that there are
eight DAC clock edges before and after the DATACLK until the
next DATACLK latching edge. With 4× interpolation, there are
only four latching edges of DACCLK available before and after
each DATACLK edge. Therefore, in 4× interpolation, only the
even numbered values for DATAADJ are available, and the
options are changed from +3 cycles to –4 cycles. With 2×
interpolation, there are only two edges available before and after
DATACLK, so the choices for DATAADJ are diminished to +1
cycle to –2 cycles.
DACCLK
LATCHING EDGE
DATA TRANSITION
Figure 42. DATAADJ = 0000
Figure 43 shows the same conditions, but now DATAADJ is set
to 1111. This moves DATACLK to the left in the plot, indicating
that it occurs one DACCLK cycle before it did in Figure 42. As
explained previously, the latching edge of DACCLK also moves
one cycle back in time.
RISING EDGE OF DATACLK
CONCURRENT WITH
LATCHING EDGE OF DACCLK
DACCLK
LATCHING EDGE
DATA TRANSITION
Figure 43. DATAADJ = 1111
Rev. PrC | Page 26 of 52