AD9259 Datasheet, PDF (26/52 Pages) Analog Devices – Quad, 14-bit, 50 MSPS Serial LVDS 1.8 V A/D Converter

AD9259
85
80
83
SFDR
81
75
79
SNR
77
70
75
73
65
71
69
60
67
65
55
2
6
10
14
18
22
RESISTANCE (kΩ)
Figure 53. SFDR vs. RBIAS
600
500
400
300
200
100
0
2
6
10
14
18
22
RESISTANCE (kΩ)
Figure 54. IAVDD vs. RBIAS
Voltage Reference
A stable and accurate 0.5 V voltage reference is built into the
AD9259. This is gained up by a factor of 2 internally, setting
VREF to 1.0 V, which results in a full-scale differential input span
of 2 V p-p. The VREF is set internally by default; however, the
VREF pin can be driven externally with a 1.0 V reference to
achieve more accuracy.
When applying the decoupling capacitors to the VREF, REFT,
and REFB pins, use ceramic low ESR capacitors. These capacitors
should be close to the ADC pins and on the same layer of the
PCB as the AD9259. The recommended capacitor values and
configurations for the AD9259 reference pin can be found in
Figure 55.
Table 12. Reference Settings
Selected
Mode
External
Reference
Internal,
2 V p-p FSR
SENSE
Voltage
AVDD
Resulting
VREF (V)
N/A
AGND to 0.2 V 1.0
Resulting
Differential
Span (V p-p)
2 × external
reference
2.0
Internal Reference Operation
A comparator within the AD9259 detects the potential at the
SENSE pin and configures the reference. If SENSE is grounded,
the reference amplifier switch is connected to the internal
resistor divider (see Figure 55), setting VREF to 1 V.
The REFT and REFB pins establish their input span of the ADC
core from the reference configuration. The analog input full-
scale range of the ADC equals twice the voltage at the reference
pin for either an internal or an external reference configuration.
If the reference of the AD9259 is used to drive multiple
converters to improve gain matching, the loading of the refer-
ence by the other converters must be considered. Figure 57
depicts how the internal reference voltage is affected by loading.
VIN+
VIN–
V_REF
1µF
0.1µF
SENSE
SELECT
LOGIC
ADC
CORE
REFT
0.1µF
0.1µF
REFB
0.1µF
+
2.2µF
0.5V
Figure 55. Internal Reference Configuration
VIN+
VIN–
EXTERNAL
REFERENCE
V_REF
1µF¹
0.1µF¹
AVDD
SENSE
SELECT
LOGIC
ADC
CORE
REFT
0.1µF
0.1µF
REFB
0.1µF
+
2.2µF
0.5V
1_OPTIONAL.
Figure 56. External Reference Operation
Rev. 0 | Page 26 of 52