AD7366-5_15 Datasheet, PDF (26/29 Pages) Analog Devices – True Bipolar Input, 12-/14-Bit, 2-Channel, Simultaneous Sampling SAR ADCs

AD7366-5/AD7367-5 TO ADSP-BF53x
The ADSP-BF53x family of DSPs interfaces directly to the
AD7366-5/AD7367-5 with no glue logic required. The availability
of secondary receive registers on the serial ports of the Blackfin®
DSPs means that only one serial port is necessary to read from
both DOUTA and DOUTB pins simultaneously. Figure 30 shows
DOUTA and DOUTB of the AD7366-5/AD7367-5 connected to
Serial Port 0 of the ADSP-BF53x. The SPORT0 Receive
Configuration 1 register and SPORT0 Receive Configuration 2
register should be set up as outlined in Table 13 and Table 14.
AD7366-5/
AD7367-5*
D_OUTA
SCLK
CS
BUSY
CNVST
D_OUTB
V_DRIVE
SERIAL
DEVICE A
(PRIMARY)
SERIAL
DEVICE B
(SECONDARY)
ADSP-BF53x*
SPORT0
DR0PRI
RCLKO
RFS0
RXINPUTS
PFn
DR0SEC
*ADDITIONAL PINS OMITTED FOR CLARITY.
V_DD
Figure 30. Interfacing the AD7366-5/AD7367-5 to the ADSP-BF53x
Table 13. SPORT0 Receive Configuration 1 Register
(SPORT0_RCR1) Setup
Setting
Description
RCKFE = 1
Sample data with falling edge of RSCLK.
LRFS = 1
Active low frame signal.
RFSR = 1
Frame every word.
IRFS = 1
Internal RFS used.
RLSBIT = 0
Receive MSB first.
RDTYPE = 00
Zero fill.
IRCLK = 1
Internal receive clock.
RSPEN = 1
Receive enabled.
SLEN = 1111
16-bit data-word (or can be set to 1101 for
14-bit data-word).
TFSR = RFSR = 1
Table 14. SPORT0 Receive Configuration 2 Register
(SPORT0_RCR2) Setup
Setting
Description
RXSE = 1
Secondary side enabled.
SLEN = 1111 16-bit data-word (or can be set to 1101 for
14-bit data-word).
AD7366-5/AD7367-5
AD7366-5/AD7367-5 TO TMS320VC5506
The serial interface on the TMS320VC5506 uses a continuous
serial clock and frame synchronization signals to synchronize
the data transfer operations with peripheral devices like the
AD7366-5/AD7367-5. The CS input allows easy interfacing
between the TMS320VC5506 and the AD7366-5/AD7367-5
with no glue logic required. The serial ports of the TMS320VC5506
are set up to operate in burst mode with internal CLKX0 (Tx
serial clock on Serial Port 0) and FSX0 (Tx frame sync from
Serial Port 0). The connection diagram is shown in Figure 31.
The serial port control registers (SPC) must be setup as shown
in Table 15.
AD7366-5/
AD7367-5*
SCLK
D_OUTA
D_OUTB
CS
BUSY
CNVST
V_DRIVE
TMS320VC5506*
CLKX0
CLKR0
CLKX1
CLKR1
DR0
DR1
FSX0
FSR0
FSR1
INTn
XF
*ADDITIONAL PINS OMITTED FOR CLARITY.
V_DD
Figure 31. Interfacing the AD7366-5/AD7367-5 to the TMS320VC5506
Table 15. Serial Port Control Register Setup
SPC
FO
FSM
MCM
TXM
SPC0
0
1
1
1
SPC1
0
1
0
0
The VDRIVE pin of the AD7366-5/AD7367-5 takes the same
supply voltage as that of the TMS320VC5506. This allows the
ADC to operate at a higher voltage than its serial interface and,
therefore, the TMS320VC5506, if necessary.
As with the previous interfaces, conversion can be initiated
from the TMS320VC5506 or from an external source, and the
processor is interrupted when the conversion sequence is
complete.
Rev. B | Page 25 of 28