AD7148 Datasheet, PDF (26/56 Pages) Analog Devices – Programmable Touch Controller for Single Electrode Capacitance Sensors

AD7148
INTERRUPT OUTPUT
The AD7148 has an interrupt output that triggers an interrupt
service routine on the host processor. The INT signal is on
Pin 12 and is an open-drain output. There are two types of
interrupt events on the AD7148: a CDC conversion complete
interrupt and a sensor threshold interrupt. Each interrupt has
enable and status registers. The conversion complete and sensor
threshold interrupts can be enabled on a per conversion stage
basis. The status registers indicate what type of interrupt triggered
the INT pin. Status registers are cleared, and the INT signal is
reset high during a read operation. The signal returns high as
soon as the read address is set up.
CDC CONVERSION-COMPLETE INTERRUPT
The AD7148 interrupt signal asserts low to indicate the
completion of a conversion stage, and new conversion result
data is available in the registers.
The interrupt can be independently enabled for each conversion
stage. Each conversion-stage-complete interrupt can be enabled
via the STAGEx_COMPLETE_INT_EN register (Address 0x007).
This register has a bit that corresponds to each conversion stage.
Setting this bit to 1 enables the interrupt for that stage. Clearing this
bit to 0 disables the conversion complete interrupt for that stage.
In normal operation, the interrupt is enabled only for the last stage
in a conversion sequence. For example, if there are five conversion
stages, the conversion-complete interrupt for STAGE4 is enabled.
INT asserts only when all five conversion stages are complete, and
the host can read new data from all five results registers. The inter-
rupt is cleared by reading the STAGEx_COMPLETE_INT_
STATUS register located at Address 0x00A.
Register 0x00A is the conversion-complete interrupt status register.
Each bit in this register corresponds to a conversion stage. If a
bit is set, it means that the conversion-complete interrupt for
the corresponding stage has been triggered. This register is
cleared on a read, provided that the underlying condition that
triggered the interrupt has gone away.
SENSOR TOUCH INTERRUPT
The sensor touch interrupt mode is implemented when the host
processor requires an interrupt only when a sensor is contacted.
Configuring the AD7148 into this mode results in the interrupt
being asserted when the user makes contact with the sensor and
again when the user lifts off the sensor. The second interrupt is
required to alert the host processor that the user is no longer
contacting the sensor.
The registers located at Address 0x005 (STAGEx_LOW_INT_EN)
and Address 0x006 (STAGEx_HIGH_INT_EN) are used to enable
the interrupt output for each stage. The registers located at
Address 0x008 (STAGEx_LOW_LIMIT_INT) and Address 0x009
(STAGEx_HIGH_LIMIT_INT) are used to read back the interrupt
status for each stage.
Figure 36 shows the interrupt output timing during contact with
one of the sensors connected to STAGE0 while operating in the
sensor touch interrupt mode. For a low limit configuration, the
interrupt output is asserted as soon as the sensor is contacted and
again after the user has stopped contacting the sensor.
Note that the interrupt output remains low until the host processor
reads back the interrupt status registers located at Address 0x008
and Address 0x009.
The interrupt output is asserted when there is a change in the
threshold status bits. This change indicates that a user is now
touching the sensor(s) for the first time, the number of sensors
being touched has changed, or the user is no longer touching
the sensor(s). Reading the status bits in the interrupt status
register shows the current sensor activations.
CONVERSION
STAGE
STAGE0
STAGE1
SERIAL
READBACK
2
4
INT OUTPUT
NOTES:
1. USER TOUCHING DOWN ON SENSOR
2. ADDRESS 0x008 READ BACK TO CLEAR INTERRUPT
3. USER LIFTING OFF OF SENSOR
4. ADDRESS 0x008 READ BACK TO CLEAR INTERRUPT
Figure 36. Example of Sensor Touch Interrupt
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