ADV7185 Datasheet, PDF (25/40 Pages) Analog Devices – Professional NTSC/PAL Video Decoder with 10-Bit CCIR656 Output

Table IX. Extended Output Control Register (Subaddress 04)
Bit Description
RANGE ¹
RESERVED
DDOS[2:0] ²
BT656-4 ⁴
Bit 7
0
1
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
1
Bit 2
1
Bit 1
0
Bit 0
0
1
Register Setting
CCIR-Compliant
Fill Whole Accessible Range
No Additional Data³
BT656-3-Compatible
BT656-4-Compatible
NOTES
1_{Allows the user to select the range of output values. Can be CCIR601-compliant or fill the whole accessible number range.}
2_{D Data Output Selection. If the 100-pin package is used, the 12 additional pins can output additional data.}
3_{12 Pins Three-State}
4_{Allows the user to select an output mode that is compatible with BT656-4 or BT656-3.}
Table X. General-Purpose Output Register (Subaddress 05)
ADV7185
Bit Description
GPO[3:0]¹
GPEL ²
GPEH³
BL_C_VBI ⁴
HL_EN^{5, 6}
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting
0 0 0 0 User Programmable
Pixel Data Valid Off
0
GPO[1:0] Three-Stated
1
GPO[1:0] Enabled
0
GPO[3:2] Three-Stated
1
GPO[3:2] Enabled
0
Decode and Output Color DuringVBI
1
Blank Cr and Cb Data DuringVBI
0
GPO[0] Pin Function
1
GPO[0] Shows HLOCK Status
NOTES
1_{Pixel Data Valid Off. These general-purpose output pins may be programmed by the user but are only available in selected output modes OF_SEL[3:0] and when the}
output drivers are enabled using GPEL, GPEH, and HL_Enable bits.
2_{General-Purpose Enable Low. Enables the output drivers for the general-purpose outputs Bits 0 and 1.}
3_{General-Purpose Enable High. Enables the output drivers for the general-purpose outputs Bits 2 and 3.}
4_{Blank Chroma during VBI.}
5_{Hlock Enable. This bit causes the GPO[0] pin to output Hlock instead of GPO[0]. Only available in certain output modes.}
6_{GPO lower bits must be enabled GPEL. Disabled.}
Table XI. FIFO Control Register (Subaddress 07)
Bit Description
FFM[4:0] ¹
FR²
AFR⁴
FFST⁵
Bit 7
0
1
Bit 6
0
1
Bit 5
0
1
Bit 4
0
Bit 3
0
Bit 2
1
Bit 1
0
Bit 0
0
Register Setting
User-Programmable
Normal Operation
FIFO Reset³
No Auto Reset
Auto Reset
Synchronous to CLKIN
Synchronous to 27 MHz
NOTES
1_{FIFO Flag Margin. Allows the user to program the location at which the FIFO flags AEF and AFF.}
2_{FIFO Reset. Setting this bit will cause the FIFO to reset.}
3_{Bit is auto-cleared.}
4_{Automatic FIFO Reset. Setting this bit will cause the FIFO to automatically reset at the end of each field of video.}
5_{FIFO Flag Self Time. Sets whether the FIFO flags AEF, AFF, and HFF are output synchronous to the external CLKIN of the 27 MHz internal clock.}
Table XII. Contrast Register (Subaddress 08)
Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting
CON[7:0]*
10000000
*Contrast Adjust. This is the user control for contrast adjustment.
REV. 0
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