ADV7175A Datasheet, PDF (25/52 Pages) Analog Devices – High Quality, 10-Bit, Digital CCIR-601 to PAL/NTSC Video Encoder

CLOSED CAPTIONING EVEN FIELD
DATA REGISTER 1–0 (CED15–CED00)
(Address [SR4–SR0] = 09–08H)
These 8-bit wide registers are used to set up the closed captioning
extended data bytes on even fields. Figure 36 shows how the
high and low bytes are set up in the registers.
BYTE 1 CED15 CED14 CED13 CED12 CED11 CED10 CED9 CED8
BYTE 0 CED7 CED6 CED5 CED4 CED3 CED2 CED1 CED0
Figure 36. Closed Captioning Extended Data Register
CLOSED CAPTIONING ODD FIELD
DATA REGISTER 1–0 (CCD15–CCD00)
(Subaddress [SR4–SR0] = 0B–0AH)
These 8-bit wide registers are used to set up the closed captioning
data bytes on odd fields. Figure 37 shows how the high and low
bytes are set up in the registers.
BYTE 1 CCD15 CCD14 CCD13 CCD12 CCD11 CCD10 CCD9 CCD8
BYTE 0 CCD7 CCD6 CCD5 CCD4 CCD3 CCD2 CCD1 CCD0
Figure 37. Closed Captioning Data Register
TIMING REGISTER 1 (TR17–TR10)
(ADDRESS [SR4–SR0] = 0CH)
Timing Register 1 is an 8-Bit Wide Register
Figure 38 shows the various operations under the control of
Timing Register 1. This register can be read from as well as
written to. This register can be used to adjust the width and
position of the master mode timing signals.
ADV7175A/ADV7176A
TR1 BIT DESCRIPTION
HSYNC Width (TR11–TR10)
These bits adjust the HSYNC pulsewidth.
HSYNC to VSYNC/FIELD Delay Control (TR13–TR12)
These bits adjust the position of the HSYNC output relative to
the FIELD/VSYNC output.
HSYNC to FIELD Delay Control (TR15–TR14)
When the ADV7175A/ADV7176A is in Timing Mode 1, these
bits adjust the position of the HSYNC output relative to the
FIELD output rising edge.
VSYNC Width (TR15–TR14)
When the ADV7175A/ADV7176A is in Timing Mode 2, these
bits adjust the VSYNC pulsewidth.
HSYNC to Pixel Data Adjust (TR17–TR16)
This enables the HSYNC to be adjusted with respect to the
pixel data. This allows the Cr and Cb components to be
swapped. This adjustment is available in both master and slave
timing modes.
MODE REGISTER 2 MR2 (MR27–MR20)
(Address [SR4-SR0] = 0DH)
Mode Register 2 is an 8-bit wide register.
Figure 39 shows the various operations under the control of Mode
Register 2. This register can be read from as well as written to.
MR2 BIT DESCRIPTION
Square Pixel Mode Control (MR20)
This bit is used to set up square pixel mode. This is available in
slave mode only. For NTSC, a 24.54 MHz clock must be sup-
plied. For PAL, a 29.5 MHz clock must be supplied.
TR17
TR16
TR15
TR14
TR13
TR12
TR11
TR10
HSYNC TO PIXEL
DATA ADJUSTMENT
TR17 TR16
00
01
10
11
0 x T_PCLK
1 x T_PCLK
2 x T_PCLK
3 x T_PCLK
HSYNC TO FIELD
RISING EDGE DELAY
(MODE 1 ONLY)
TR15 TR14
x0
x1
T_C
T_B
T_B + 32␮s
VSYNC WIDTH
(MODE 2 ONLY)
TR15 TR14
0
0
0
1
1
0
1
1
1 x T_PCLK
4 x T_PCLK
16 x T_PCLK
128 x T_PCLK
TIMING MODE 1 (MASTER/PAL)
LINE 1
HSYNC
T_A
T_B
FIELD/VSYNC
HSYNC TO
FIELD/VSYNC DELAY
TR13 TR12
00
01
10
11
T_B
0 x T_PCLK
4 x T_PCLK
8 x T_PCLK
16 x T_PCLK
HSYNC WIDTH
TR11 TR10
T_A
0
0 1 x T_PCLK
0
1 4 x T_PCLK
1
0 16 x T_PCLK
1
1 128 x T_PCLK
LINE 313
T_C
LINE 314
Figure 38. Timing Register 1
REV. B
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