ADAU1382 Datasheet, PDF (25/84 Pages) Analog Devices – Low Noise Stereo Codec with Recording and Playback Processing

ADAU1382
STARTUP, INITIALIZATION, AND POWER
This section details the procedure for setting up the ADAU1382
properly. Figure 26 provides an overview of how to initialize the IC.
START
ARE AVDD1 AND AVDD2
SUPPLIED SEPARATELY?
YES
NO
SUPPLY POWER TO AVDD1/AVDD2
PINS SIMULTANEOUSLY
CAN AVDD1 AND AVDD2
NO
BE SIMULTANEOUSLY
SUPPLIED?
YES
SUPPLY POWER
TO AVDD1
SUPPLY POWER
TO AVDD2
SUPPLY POWER TO IOVDD
WAIT 14ms FOR POWER-ON RESET
AND INITIALIZATION ROM BOOT
CONFIGURE CLOCK GENERATION
REGISTER 16384 (0x4000)
AND REGISTER 16386 (0x4002)
WAIT FOR PLL LOCK
(2.4ms TO 3.5ms)
ENABLE DIGITAL POWER TO
FUNCTIONAL SUBSYSTEMS
REGISTER 16512 (0x4080)
AND REGISTER 16513 (0x4081)
POWER-UP SEQUENCE
If AVDD1 and AVDD2 are from the same supply, they can
power up simultaneously. If AVDD1 and AVDD2 are from
separate supplies, then AVDD1 should be powered up first.
IOVDD should be applied simultaneously with AVDD1, if
possible.
The ADAU1382 uses a power-on reset (POR) circuit to reset the
registers upon power-up. The POR monitors the DVDDOUT
pin and generates a reset signal whenever power is applied to
the chip. During the reset, the ADAU1382 is set to the default
values documented in the register map (see the Control Register
Map section).
The POR is also used to prevent clicks and pops on the speaker
driver output. The power-up sequencing and timing involved is
described in Figure 27 in this section, and in Figure 35
and Figure 36 of the Speaker Output section.
A self-boot ROM initializes the memories after the POR has
completed. When the self-boot sequence is complete, the control
registers are accessible via the I²C/SPI control port and should
then be configured as required for the application. Typically,
with a 10 μF capacitor on AVDD1, the power supply ramp-up,
POR, and self-boot combined take approximately 14 ms.
SET UP SOUND ENGINE REGISTERS
FOR CUSTOMIZED SIGNAL PATH
(INCLUDING VOLUME, SAMPLE RATES,
FILTER COEFFICIENTS)
INITIALIZATION
COMPLETE
Figure 26. Initialization Sequence
MAIN SUPPLY ENABLED
MAIN SUPPLY DISABLED
AVDD1
1.5V
AVDD2
DVDDOUT
POWER-UP
(INTERNAL
SIGNAL)
IOVDD
INTERNAL MCLK
(NOT TO SCALE)
1.5V
1.35V
0.95V
POR
ACTIVE
POR ACTIVATES
POR COMPLETE/SELF-BOOT INITIATES
SELF-BOOT COMPLETE/MEMORY
IS ACCESSIBLE
14ms
INPUT/OUTPUT
PINS
HIGH-Z
ACTIVE
HIGH-Z
Figure 27. Power-Up and Power-Down Sequence Timing Diagram
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