AD9626 Datasheet, PDF (25/36 Pages) Analog Devices – 12-Bit, 170 MSPS/210 MSPS/250 MSPS, 1.8 V Analog-to-Digital Converter

AD9626
MEMORY MAP
READING THE MEMORY MAP TABLE
Each row in the memory map table has eight address locations.
The memory map is roughly divided into three sections: chip
configuration register map (Address 0x00 to Address 0x02),
transfer register map (Address 0xFF), and program register map
(Address 0x08 to Address 0x2A).
The Addr (Hex) column of the memory map indicates the
register address in hexadecimal, and the Default Value (Hex)
column shows the default hexadecimal value that is already
written into the register, The Bit 7 (MSB) column is the start of
the default hexadecimal value given. For example, Hexadecimal
Address 0x09, clock, has a hexadecimal default value of 0x01.
This means Bit 7 = 0, Bit 6 = 0, Bit 5 = 0, Bit 4 = 0, Bit 3 = 0,
Bit 2 = 0, Bit 1 = 0, and Bit 0 = 1, or 0000 0001 in binary. The
default value enables the duty cycle stabilizer. Overwriting this
default so that Bit 0 = 0 disables the duty cycle stabilizer. For more
information on this and other functions, consult the Interfacing
to High Speed ADCs via SPI user manual at www.analog.com.
RESERVED LOCATIONS
Undefined memory locations should not be written to other
than their default values suggested in this data sheet. Addresses
that have values marked as 0 should be considered reserved and
have a 0 written into their registers during power-up.
DEFAULT VALUES
Coming out of reset, critical registers are preloaded with default
values. These values are indicated in Table 12. Other registers
do not have default values and retain the previous value when
exiting reset.
LOGIC LEVELS
An explanation of various registers follows: “Bit is set” is
synonymous with “bit is set to Logic 1” or “writing Logic 1 for
the bit.” Similarly, “clear a bit” is synonymous with “bit is set to
Logic 0” or “writing Logic 0 for the bit.”
Table 12. Memory Map Register
Addr
Bit 7
(Hex) Parameter Name (MSB)
Chip Configuration Registers
00
chip_port_config 0
01
chip_id
02
chip_grade
0
Transfer Register
FF
device_update
0
ADC Functions
08
modes
0
Bit 6 Bit 5
LSB Soft reset
first
0
0
0
0
0
PDWN:
0 = full
(default)
1=
standby
Bit 4
Bit 3 Bit 2
Bit 1
Bit 0
(LSB)
Default
Value Default Notes/
(Hex) Comments
1
1
Soft reset LSB
0
first
8-bit chip ID, Bits[7:0]
AD9626 = 0x3c
Speed grade: X
00 = 170 MSPS
01 = 210 MSPS
10 = 250 MSPS
X
X
0x18
Read-
only
Read-
only
The nibbles should
be mirrored by the
user so that LSB or
MSB first mode
registers correctly,
regardless of shift
mode.
Default is unique
chip ID, different
for each device.
This is a read-only
register.
Child ID used to
differentiate
graded devices.
0
0
0
0
SW
0x00
Synchronously
transfer
transfers data from
the master shift
register to the
slave.
0
0
Internal power-down mode:
0x00
Determines various
000 = normal (power-up, default)
001 = full power-down
generic modes of
chip operation.
010 = standby
011 = normal (power-up)
Note: external PDWN pin overrides
this setting
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