AD7999_15 Datasheet, PDF (25/28 Pages) Analog Devices – 4-Channel, 12-/10-/8-Bit ADC with IC-Compatible Interface in 8-Lead SOT-23

AD7991/AD7995/AD7999
PLACING THE AD7991/AD7995/AD7999 INTO HIGH SPEED MODE
High speed mode communication commences after the master
All devices continue to operate in high speed mode until the
addresses all devices connected to the bus with the master code,
master issues a stop condition. When the stop condition is
00001XXX, to indicate that a high speed mode transfer is to
issued, the devices return to fast mode.
begin. No device connected to the bus is allowed to acknowledge
the high speed master code; therefore, the code is followed by a
NO ACK (see Figure 26). The master must then issue a repeated
start, followed by the device address and an R/W bit. The selected
device then acknowledges its address.
To guarantee performance above fSCL = 1.7 MHz, the user must
perform clock stretching—that is, the clock must be held high—for
2 μs after the ninth clock rising edge (see Figure 27). Therefore,
the clock must be held high for 2 μs after the device starts to power
up (see the Reading from the AD7991/AD7995/AD7999 section).
1
SCL
FAST MODE
9
1
HIGH SPEED MODE
9
SDA
0
START BY
MASTER
0
0
0
1
XXX
NO ACK Sr
HS MODE MASTER CODE
01
0
1
0
0 A0
SERIAL BUS ADDRESS BYTE
ACK BY
ADC
Figure 26. Placing the Part into High Speed Mode
CLOCK HIGH TIME = 2µs
1
SCL
9
1
9
SDA
0
START BY
MASTER
1
0
1
0
0 A0 R/W
0
ACK BY
ADC
FRAME 1
SERIAL BUS ADDRESS BYTE
1
SCL (CONTINUED)
0
D11 D10 D9 D8
CH_ID1 CH_ID0
ACK BY
MASTER
FRAME 2
MOST SIGNIFICANT DATA BYTE FROM ADC
9
SDA (CONTINUED)
D7 D6 D5 D4 D3 D2 D1 D0
NO ACK BY
MASTER
FRAME 3
LEAST SIGNIFICANT DATA BYTE FROM ADC
STOP BY
MASTER
Figure 27. Reading Two Bytes of Data from the Conversion Result Register in High Speed Mode for AD7991
Rev. B | Page 25 of 28