AD7877_15 Datasheet, PDF (25/45 Pages) Analog Devices – Touch Screen Controller

AD7877
HOST PROGRAMS
AD7877 IN MODE 11
GO TO MODE 00
NO
VALID
SEQUENCE 1?
YES
IS
SCREEN
NO
TOUCHED?
YES
SELECT NEXT
CHANNEL
IS FCD
NO
REQUIRED?
YES
START FCD TIMER
IS FCD
NO
FINISHED?
YES
YES
IS STOPACQ
SIGNAL ACTIVE?
NO
START ACQUISITION TIMER
YES
IS STOPACQ
SIGNAL ACTIVE?
NO
IS ACQUISITION
TIME FINISHED? _NO
YES
CONVERT
SELECTED CHANNEL
IS AVERAGING ^NO
FINISHED?
YES
WRITE RESULT TO
REGISTERS
LIMIT COMPARISON
NO
OUT-OF-LIMIT?
YES
UPDATE ALERT
ENABLE/STATUS
REGISTER
ALERT
SOURCE
NO
ENABLED?
YES
ASSERT ALERT
OUTPUT¹
LAST CHANNEL
NO
IN SEQUENCE?
YES
YES
ONCE-ONLY
MODE?
NO
IS
SCREEN STILL ^NO
TOUCHED?
YES
START TIMER
TIMER
YES
FINISHED?
NO
YES
IS
SCREEN STILL
NO
TOUCHED?
1_{SEE SEQUENCER REGISTERS SECTION.}
Figure 40. Master Mode Sequencer Operation
Data Sheet
INTERRUPTS
Data Available Output (DAV)
The data available output (DAV) indicates that new ADC data
is available in the results registers. While the ADC is idle or is
converting, DAV is high. Once the ADC has finished converting
and new data has been written to the results registers, DAV goes
low. Taking DAV low to read the registers resets DAV to a high
condition. DAV is also reset, if a new conversion is started by
the AD7877 because the timer expired. The host should attempt
to read the results registers only when DAV is low.
CS
DAV
AD7877
STATUS IDLE
SETUP
BY HOST
t_CONV
ADC
CONVERTING
NEW DATA HOST READS
AVAILABLE RESULTS
IDLE
Figure 41. Operation of DAV Output
DAV is useful as a host interrupt in master mode. In this mode,
the host can program the AD7877 to automatically perform a
sequence of conversions, and can be interrupted by DAV at the
end of each conversion sequence.
When the on-board timer is programmed to perform automatic
conversions, a limited time is available to the host to read the
results registers before another sequence of conversions begins.
The DAV signal is reset high when the timer expires, and the
host should not access the results registers while DAV is high.
Figure 42 shows the worst-case timings for reading the results
registers after DAV has gone low. The timer is set at a
minimum, and the conversion sequence includes all 11 possible
ADC channels. t1 is the time taken for acquisition and
conversion on one ADC channel. t2 shows the minimum timer
delay, that is, 1024 clock periods. t3 is the time taken to read all
11 result registers. If the host wants to read all 11 registers, then
it must do so before the timer expires. t4 is the maximum time
allowable between DAV going low and the host beginning to
read the results registers. If t4 is exceeded, then all registers
cannot be read before the start of a new conversion, and
incorrect data could be read by the host.
AD7877
STATUS
DAV
t₁
CHANNEL 11
CONVERSION AND
ACQUISITION
t₂
TIMER INTERVAL
CHNL
1
CS
DOUT
t₄
t₃
Figure 42. Timing for Reads after DAV Goes Low
Rev. D | Page 24 of 44