AD1816A_15 Datasheet, PDF (25/52 Pages) Analog Devices – SoundPort Controller

AD1816A
[Base+4] PIO Debug
7
6
RES
5
PUR
4
COR
3
2
ORR[1:0]
1
0
ORL[1:0]
RESET = [0x00]
All bits in this register are sticky until any write that clears all bits to 0.
ORL/ORR (RO)
[1:0]
Overrange Left/Right detect. These bits record the largest output magnitude on the ADC right and left
channels and are cleared to 00 after any write to this register. The peak amplitude as recorded by these bits is
“sticky,” i.e., the largest output magnitude recorded by these bits will persist until these bits are explicitly
cleared. They are also cleared by powering down the chip.
ORL/ORR Over/Under Range Detection
00
Less than –1 dB Underrange
OBSOLETE ⁰¹
Between –1 dB and 0 dB Underrange
10
Between 0 dB and 1 dB Overrange
11
Greater than 1 dB Overrange
COR
PUR
[Base+5]
(RO)
Capture Over Run. The codec sets (1) this bit when capture data is not read within one sample period after the
capture FIFO fills. When COR is set, the FIFO is full and the codec discards any new data generated. The
codec clears this bit immediately after a 4 byte capture sample is read.
(RO)
Playback Under Run. The codec sets (1) this bit when playback data is not written within one sample period af-
ter the playback FIFO empties. The codec clears (0) this bit immediately after a 4 byte playback sample is writ-
ten. When PUR is set, the playback channel has “run out” of data and either plays back a midscale value or
repeats the last sample.
PIO Status
7
PFH
6
PDR
5
PLR
4
PUL
3
CFH
2
CDR
1
CLR
0
CUL
RESET = [0x00]
CUL
(RO) Capture Upper/Lower Sample. This bit indicates whether the PIO capture data ready is for the upper
or lower byte of the channel.
0 Lower byte ready
1 Upper byte ready or any 8-bit mode
CLR
(RO)
Capture Left/Right Sample. This bit indicates whether the PIO capture data waiting is for the left channel ADC
or the right channel ADC.
0 Right channel
1 Left channel or mono
CDR
(RO)
Capture Data Ready. The PIO Capture Data register contains data ready for reading by the host. This bit should be
used only when direct programmed I/O data transfers are desired (FIFO has at least 4 bytes before full).
0 ADC is stale. Do not reread the information
1 ADC data is fresh. Ready for next host data read
CFH
(RO) Capture FIFO Half Full. (FIFO has at least 32 bytes before full.)
PUL
(RO)
Playback Upper/Lower Sample. This bit indicates whether the PIO playback data needed is for the upper or
lower byte of the channel.
0 Lower byte needed
1 Upper byte needed or any 8-bit mode
PLR
(RO) Playback Left/Right Sample. This bit indicates whether the PIO playback data needed is or the left channel
DAC or the right channel DAC.
0 Right channel needed
1 Left channel or mono
PDR
(RO)
Playback Data Ready. The PIO Playback data register is ready for more data. This bit should only be used
when direct programmed I/O data transfers are desired (FIFO can take at least 4 bytes).
0 DAC data is still valid. Do not overwrite
1 DAC data is stale. Ready for next host data write value
PFH
(RO) Playback FIFO Half Empty. FIFO can take at least 32 bytes, eight groups of 4 bytes.
REV. A
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