A3983_08 Datasheet, PDF (25/32 Pages) Allegro MicroSystems – DMOS Microstepping Driver with Translator

AD1888
Table 40. Jack Sense/Audio Interrupt Status Register (Index 72h)
Reg
No. Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default
72h Jack JS1 JS1 JS0 JS JS JS X X JS1 JS0 JS1 JS0 JS1 JS0 JS1 JS0 0000h
Sense SPRD DMX DMX MT2 MT1 MT0
TMR TMR MD MD ST ST INT INT
All register bits are read/write except for JS0ST and JS1ST, which are read only.
JS0INT
JS1INT
JS0ST
JS1ST
JS0MD
JS1MD
JS0TMR
JS1TMR
JSMT[2,0]
JS0DMX
JS1DMX
JS1SPRD
Indicates Pin JS0 has generated an interrupt. Remains set until the software services JS0 interrupt, i.e., JS0 ISR should clear this
bit by writing a 0 to it. Note that the interrupt to the system is actually an OR combination of this bit and JS1INT. Also, note that
the actual interrupt implementation is selected by the INTS bit (Register 76h).
It is also possible to generate a software system interrupt by writing a 1 to this bit.
Indicates Pin JS1 has generated an interrupt. Remains set until the software services JS1 interrupt, i.e., JS1 ISR should clear this
bit by writing a 0 to it. See the JS0INT description for additional details.
JS0 STATE. This bit always reports the logic state of the JS0 pin.
JS1 STATE. This bit always reports the logic state of the JS1 pin.
JS0 Mode. This bit selects the operation mode for the JS0 pin.
0 = Jack Sense Mode (reset default)
1 = Interrupt Mode
JS1 Mode. This bit selects the operation mode for the JS1 pin.
0 = Jack Sense Mode (reset default)
1 = Interrupt Mode
JS0 Timer Enable. If this bit is set to a 1, JS0 must be high for greater than 278 ms to be recognized.
JS1 Timer Enable. If this bit is set to a 1, JS1 must be high for greater than 278 ms to be recognized.
JS Mute Enable Selector. These three bits select and enable the Jack Sense muting action (see Table 41).
JS0 Down Mix Control Enable. This bit enables JS0 to control the down-mix function. This function allows a digital mix of six
channels of audio into 2-channel audio. The mix can then be routed to the stereo Line_OUT or HP_OUT jacks. When this bit is
set to 1, JS0 = 1 will activate the down-mix conversion. See the DMIX description in Register 76h. The DMIX bits select the
down-mix implementation type and can also force the function to be activated.
JS1 Down Mix Control Enable. This bit enables 2-channel to 6-channel audio spread function when both Jack Senses are active
(logic state 1).
Note that the SPRD bit can also force the spread function without being gated by the Jack Senses. See this bit’s description in
Register 76h for a better understanding of the spread function.
JS Spread Control Enable. This bit enables 2-channel to 6-channel audio spread function when both Jack Senses are active
(logic state 1).
Note that the SPRD bit can also force the spread function without being gated by the Jack Senses. See this bit’s description in
Register 76h for a better understanding of the spread function.
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