HMC832 Datasheet, PDF (24/49 Pages) Analog Devices – Cellular infrastructure

Data Sheet
HMC832
Table 8. Reference Sensitivity
Reference Input
Frequency (MHz)
<10
10
25
50
100
150
200
Slew > 0.5 V/ns
Recommended
Yes
Yes
Yes
Yes
Yes
Okay
Okay
Square Input
Recommended Swing (V p-p)
Minimum
Maximum
0.6
2.5
0.6
2.5
0.6
2.5
0.6
2.5
0.6
2.5
0.9
2.5
1.2
2.5
Recommended
No
No
Okay
Yes
Yes
Yes
Yes
Sinusoidal Input
Recommended Power Range (dBm)
Minimum
Maximum
No
No
No
No
8
15
6
15
5
15
4
12
3
8
Reference Path, R Divider
The reference path, R divider is based on a 14-bit counter and
can divide input signals by values from 1 to 16,383 and is
controlled via Register 0x02.
RF Path, N Divider
The main RF path divider is capable of average divide ratios
between 2¹⁹ − 5 (524,283) and 20 in fractional mode, and 2¹⁹ − 1
(524,287) to 16 in integer mode. The VCO frequency range
divided by the minimum N divider value places practical
restrictions on the maximum usable PD frequency. For
example, a VCO operating at 1.5 GHz in fractional mode with a
minimum N divider value of 20 has a maximum PD frequency
of 75 MHz.
Lock Detect
The lock detect (LD) function verifies that the HMC832 is
generating the desired frequency. It is enabled by writing
Register 0x07[3] = 1. The HMC832 provides an LD indicator in
one of two ways
• As an output available on the LD_SDO pin of the
HMC832, (configuration is required to use the LD_SDO
pin for LD purposes, for more information, see the Serial
Port and Configuring the LD_SDO Pin for LD Output
sections).
• Or reading from Register 0x12[1], where Bit 1 = 1 indicates
a locked condition and Bit 1 = 0 indicates an unlocked
condition.
The LD circuit expects the divided VCO edge and the divided
reference edge to appear at the PD within a user specified time
period (window), repeatedly. Either signal may arrive first, only
the difference in arrival times is significant. The arrival of the
two edges within the designated window increments an internal
counter. When the count reaches and exceeds a user specified
value (Register 0x07[2:0]) the HMC832 declares lock.
Failure in registering the two edges in any one window resets
the counter and immediately declares an unlocked condition.
Lock is deemed to be reestablished when the counter reaches
the user specified value (Register 0x07[2:0]) again.
The HMC832 supports two lock detect modes:
• Analog LD, that only supports a fixed window size of 10 ns.
Analog LD mode is selected by writing Register 0x07[6] = 0.
• Digital LD, that supports a user configurable window size,
programmed in Register 0x07[11:7]. Digital LD is selected
by writing Register 0x07[6] = 1.
Lock Detect Configuration
Optimal spectral performance in fractional mode requires CP
current and CP offset current configuration discussed in detail
in the Charge Pump (CP) and Phase Detector (PD) section.
These settings in Register 0x09 impact the required LD window
size in fractional mode of operation. To function, the required
lock detect window size is provided by Equation 10 in fractional
mode and Equation 11 in integer mode.
LD Window (sec) =


I_{CP Offset} (A)
f_PD(Hz)× I_CP (A)
+ 2.66 ×10^−9(sec) +
1 _
f_PD(Hz) ^
(10)
2
LD Window (sec) = ¹
2 × f_PD
(11)
where:
fPD is the comparison frequency of the phase detector.
ICP Offset is the charge pump offset current (Register 0x09[20:14]).
ICP is the full-scale current setting of the switching charge pump
(Register 0x09[6:0] or Register 0x09[13:7]).
If the result provided by Equation 10 is equal to 10 ns, analog
LD can be used (Register 0x07[6] = 0); otherwise, digital LD is
necessary (Register 0x07[6] = 1).
Table 9 lists the required Register 0x07 settings to appropriately
program the digital LD window size. From Table 9, select the
closest value in the digital LD window size columns to the ones
calculated in Equation 10 and Equation 11, and program
Register 0x07[11:10] and Register 0x07[9:7] accordingly.
Rev. A | Page 23 of 48