EVAL-AD1871EB Datasheet, PDF (24/28 Pages) Analog Devices – Stereo Audio, 24-Bit, 96 kHz, Multibit
- ADC

AD1871
15–12
11
0011
1
Table XIV. Peak Reading Register I (Address 0011b, Read-Only)
10
9
8
7
6
5
4
3
2
0
A0P5 A0P4 A0P3 A0P2
9–6 Reserved
(Always Set to Zero)
5–0 A0P5–A0P0 Left Channel Peak Reading (Valid Only When PRE = 1)
1
A0P1
0
A0P0
15–12
0100
Table XV. Peak Reading Register II (Address 0100b, Read-Only)
11
10
9
1
0
8
7
6
5
4
3
2
1
0
A1P5 A1P4 A1P3 A1P2 A1P1 A1P0
9–6 Reserved
5–0 A1P5–A1P0
(Always Set to Zero)
Right Channel Peak Reading (Valid Only When PRE = 1)
Peak Reading Registers
The Peak Reading Registers are read-only registers that can be
enabled to track-and-hold the peak ADC reading from each
channel. The peak reading feature is enabled by setting Bit PRE
in Control Register I. The peak reading value is contained in the
six LSBs of the 10-bit readback word. The result is binary coded
where each LSB is equivalent to –1 dBFS with all zeros cor-
responding to full scale (0 dBFS) and all ones corresponding
to –63 dBFS (see Table XVI). When Bit PRE is set, the peak
reading per channel is stored in the appropriate peak register.
Once the register is read, the register value is set to zero and is
updated by subsequent conversions.
Table XVI. Peak Reading Result Format
Code
AxP 5 4 3 2 1 0
000000
000001
000010
111110
111111
Level
0 dBFS
–1 dBFS
–2 dBFS
–62 dBFS
–63 dBFS
A Peak Reading Register read cycle is detailed in Figure 21.
EXTERNAL CONTROL
The AD1871 can be configured for external hardware control of
a subset of the device functionality. This functionality includes
Master/Slave Mode select, MCLK select, and serial data
format select. External control is enabled by tying the XCTRL
Pin high as shown in Figure 22.
V_DD
AD1871
XCTRL
Figure 22. External Control Configuration
Master/Slave Select
The Master/Slave hardware select (Pin 5, CLATCH/[M/S])
is equivalent to setting the M/S Bit of Control Register II. If set
low, the device is placed in Master Mode, whereby the LRCLK
and BCLK signals are outputs from the AD1871.
When M/S is set high, the device is in Slave Mode, whereby the
LRCK and BCLK signals are inputs to the AD1871.
MCLK Mode Select
The MCLK Mode hardware select (Pin 2, CCLK/[256/512]) is
a subset of the MCLK Mode selection that is determined by
Bits CM1–CM0 of Control Register X. When the hardware pin
is low, the device operates with an MCLK that is 256 ¥ f_S; if the
pin is set high, the device operates with an MCLK that is 512 ¥ f_S.
Serial Data Format Select
The Serial Data Format hardware select (Pins 3 and 4, DF0/
COUT and DF1/CIN) is equivalent to setting Bits DF1–DF0 of
Control Register II. See Table VIII.
In External Control Mode, all functions other than those
selected by the hardware select pins (Master/Slave Mode select,
MCLK select, and Serial Data Format select) are in their
default (power-on) state.
MODULATOR MODE
When the device is in Modulator Mode (MME Bit is set to 1),
the D[0–3] pins are enabled as data outputs, while the COUT
pin becomes MODCLK, a high speed sampling clock (nomi-
nally at 128 Ï« f_S). The MODCLK enables successive data from
the left and right channel modulators with left channel modula-
tor data being valid in the low phase of MODCLK, while right
channel modulator data is valid under the high phase of MODCLK
(see Modulator Mode Timing in Figure 6).
The Modulator Mode is designed to be used for applications
such as direct stream digital (DSD) where modulator data is
stored directly to the recording media without decimation and
filtering to a lower sample rate. DSD is specified at a rate of
64 Ï« f_S, whereas the AD1871 outputs at 128 Ï« f_S,
requiring an intermediate remodulator that downsamples to
64 Ï« f_S and generates a single-bit output steam.
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