ADUM5402WCRWZ Datasheet, PDF (24/28 Pages) Analog Devices – Quad-Channel, 2.5 kV Isolators with Integrated DC-to-DC Converter

ADuM5401/ADuM5402/ADuM5403/ADuM5404
Data Sheet
The maximum external load can be calculated by subtracting
the dynamic output load from the maximum allowable load.
IISO (LOAD) = IISO (MAX) − Σ IISO ; (D)n n = 1 to 4
(2)
where:
IISO (LOAD) is the current available to supply an external secondary
side load.
IISO (MAX) is the maximum external secondary side load current
available at VISO.
IISO (D)n is the dynamic load current drawn from VISO by an input
or output channel, as shown in Figure 23 and Figure 24.
The preceding analysis assumes a 15 pF capacitive load on each
data output. If the capacitive load is larger than 15 pF, the additional
current must be included in the analysis of IDD1 and IISO . (LOAD)
POWER CONSIDERATIONS
The ADuM5401/ADuM5402/ADuM5403/ADuM5404 power
input, data input channels on the primary side, and data channels
on the secondary side are all protected from premature operation
by undervoltage lockout (UVLO) circuitry. Below the minimum
operating voltage, the power converter holds its oscillator inactive
and all input channel drivers and refresh circuits are idle. Outputs
remain in a high impedance state to prevent transmission of
undefined states during power-up and power-down operations.
During application of power to VDD1, the primary side circuitry
is held idle until the UVLO preset voltage is reached. At that
time, the data channels initialize to their default low output
state until they receive data pulses from the secondary side.
When the primary side is above the UVLO threshold, the data
input channels sample their inputs and begin sending encoded
pulses to the inactive secondary output channels. The outputs
on the primary side remain in their default low state because no
data comes from the secondary side inputs until secondary side
power is established. The primary side oscillator also begins to
operate, transferring power to the secondary power circuits.
The secondary VISO voltage is below its UVLO limit at this
point; the regulation control signal from the secondary side
is not being generated. The primary side power oscillator is
allowed to free run under these conditions, supplying the
maximum amount of power to the secondary side.
As the secondary side voltage rises to its regulation setpoint,
a large inrush current transient is present at VDD1. When the
regulation point is reached, the regulation control circuit produces
the regulation control signal that modulates the oscillator on the
primary side. The VDD1 current is then reduced and is propor-
tional to the load current. The inrush current is less than the
short-circuit current shown in Figure 14. The duration of the
inrush current depends on the VISO loading conditions and on
the current and voltage available at the VDD1 pin.
As the secondary side converter begins to accept power from the
primary, the VISO voltage starts to rise. When the secondary side
UVLO is reached, the secondary side outputs are initialized to
their default low state until data is received from the corresponding
primary side input. It can take up to 1 μs after the secondary
side is initialized for the state of the output to correlate to the
primary side input.
Secondary side inputs sample their state and transmit it to the
primary side. Outputs are valid about 1 μs after the secondary
side becomes active.
Because the rate of charge of the secondary side power supply is
dependent on loading conditions, the input voltage, and the output
voltage level selected, take care that the design allows the converter
sufficient time to stabilize before valid data is required.
When power is removed from VDD1, the primary side converter
and coupler shut down when the UVLO level is reached. The
secondary side stops receiving power and starts to discharge.
The outputs on the secondary side hold the last state that they
received from the primary side. Either the UVLO level is reached
and the outputs are placed in their high impedance state, or the
outputs detect a lack of activity from the primary side inputs and
the outputs are set to their default low value before the secondary
power reaches UVLO.
INCREASING AVAILABLE POWER
The ADuM5401/ADuM5402/ADuM5403/ADuM5404 are
designed with the capability of running in combination with
other compatible isoPower devices. The RCOUT pin allows the
ADuM5401/ADuM5402/ADuM5403/ADuM5404 to provide its
PWM signal to another device acting as a master to regulate its
self and slave devices. Power outputs are combined in parallel
while sharing output power equally.
The ADuM5401/ADuM5402/ADuM5403/ADuM5404 can only
be a master/standalone, and the ADuM5200 can only be a slave/
standalone device. The ADuM5000 can operate as either a master
or slave. This means that the ADuM5000, ADuM520x, and
ADuM540x can only be used in the master/slave combinations
listed in Table 26.
Table 26. Allowed Combinations of isoPower Parts
Slave
Master
ADuM5000 ADuM520x ADuM540x
ADuM5000 Yes
Yes
No
ADuM520x No
No
No
ADuM540x Yes
Yes
No
The allowed combinations of master and slave configured parts
listed in Table 26 is sufficient to make any combination of power
and channel count.
Rev. C | Page 24 of 28