ADSP-21062LCSZ-160 Datasheet, PDF (24/64 Pages) Analog Devices – SHARC Processor

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
Flags
Table 13. Flags
5 V and 3.3 V
Parameter
Min
Max
Timing Requirements
t_SFI
t_HFI
t_DWRFI
FLAG3–0 IN Setup Before CLKIN High¹
FLAG3–0 IN Hold After CLKIN High¹
FLAG3–0 IN Delay After RD/WR Low¹
t_HFIWR
FLAG3–0 IN Hold After RD/WR Deasserted¹
Switching Characteristics
8 + 5DT/16
0 – 5DT/16
0
5 + 7DT/16
t_DFO
FLAG3–0 OUT Delay After CLKIN High
t_HFO
FLAG3–0 OUT Hold After CLKIN High
16
4
t_DFOE
t_DFOD
CLKIN High to FLAG3–0 OUT Enable
CLKIN High to FLAG3–0 OUT Disable
3
14
1 _{Flag inputs meeting these setup and hold times for instruction cycle N will affect conditional instructions in instruction cycle N+2.}
Unit
ns
ns
ns
ns
ns
ns
ns
ns
CLKIN
FLAG3–0 OUT
t_DFOE
CLKIN
FLAG3–0 IN
RD/WR
t_SFI
t_DWRFI
FLAG INPUT
t_DFO
t_HFO
t_DFO
FLAG OUTPUT
t_HFI
t_HFIWR
Figure 13. Flags
t_DFOD
Rev. F | Page 24 of 64 | March 2008