AD9949_15 Datasheet, PDF (24/36 Pages) Analog Devices – 12-Bit CCD Signal Processor with Precision Timing Core

AD9949
H-COUNTER SYNCHRONIZATION
The H-Counter reset occurs seven CLI cycles following the HD falling edge. The PxGA steering is synchronized with the reset of the
internal H-Counter (see Figure 26).
As mentioned in the H-Counter Behavior section, the AD9949 H-counter rolls over to zero and continues counting when the maximum
counter length is exceeded. The newer AD9949A product does not roll over but holds at its maximum value until the next HD rising edge
occurs.
VD
HD
H-COUNTER
RESET
CLI
H-COUNTER _{X X}
(PIXEL COUNTER)
X
X
X
X
X
X
X
X
0
1
2
3
4
5
6
7
8
9 10 11 12 14 15 0
1
2
3
PxGA GAIN
REGISTER
X
X
X
X
X
X
X
X
X
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
2
3
2
3
NOTES
1. INTERNAL H-COUNTER IS RESET 7 CLI CYCLES AFTER THE HD FALLING EDGE (WHEN USING VDHDEDGE = 0).
2. TYPICAL TIMING RELATIONSHIP: CLI RISING EDGE IS COINCIDENT WITH HD FALLING EDGE.
3. PxGA STEERING IS SYNCRONIZED WITH THE RESET OF THE INTERNAL H-COUNTER (MOSAIC SEPARATE MODE IS SHOWN).
Figure 26. H-Counter Synchronization
Rev. B | Page 24 of 36