AD9863 Datasheet, PDF (24/40 Pages) Analog Devices – Mixed-Signal Front-End (MxFE) Baseband Transceiver for Broadband Applications

AD9863
Table 11 describes AD9863 pin function (when mode pins are used) relative to I/O mode and for half-duplex modes, whether
transmitting or receiving.
Table 11. AD9863 Pin Function vs. Interface Mode (No SPI Cases)¹
Mode Name U12 Bus
L12 Bus
IFACE1
FD
Interleaved Tx data Interleaved Rx data TxSYNC
HD12
Interleaved Tx data MSB = TxSYNC
Tx/Rx = tied high
(Tx/Rx = High)
Others = three-state
IFACE2
Buffered Rx Clock
12/24 pin control tied high
IFACE3
Buffered Tx clock
Buffered Tx clock
HD12
MSB = RxSYNC
Interleaved Rx data Tx/Rx = tied low 12/24 pin control tied high Buffered Rx clock
(Tx/Rx = Low) Others = three-state
HD24
Tx_A data
(Tx/Rx = High)
Tx_B data
Tx/Rx = tied high 12/24 pin control tied low Buffered Tx clock
HD24
Rx_B data
(Tx/Rx = Low)
Rx_A data
Tx/Rx = tied low 12/24 pin control tied low Buffered Rx clock
Clone Mode x
x
x
x
x
(Tx/Rx = High)
Clone Mode x
x
x
x
x
(Tx/Rx = Low)
1 _{Clone mode not available without SPI.}
Table 12 describes AD9863 pin function (when SPI programming is used) relative to flexible I/O mode and for half-duplex modes,
whether transmitting or receiving.
Table 12. AD9863 Pin Function vs. Interface Mode (Configured through the SPI Registers)
Mode Name
U12 Bus
L12 Bus
IFACE1
IFACE2
FD
Interleaved Tx data Interleaved Rx data TxSYNC
Buffered system
clock
HD12, Tx Mode
(Tx/Rx = High)
Interleaved Tx data MSB = TxSYNC
Tx/Rx = tied high
others = three-state
Optional buffered
system clock
HD12, Rx Mode
(Tx/Rx = Low)
MSB = RxSYNC
Interleaved Tx data
Other = three-state
Tx/Rx = tied low
Optional buffered
system clock
HD24, Tx Mode
(Tx/Rx = High)
Tx_A data
Tx_B data
Tx/Rx = tied high Optional buffered
system clock
HD24, Rx Mode
(Tx/Rx = Low)
Rx_B data
Rx_A data
Tx/Rx = tied low
Optional buffered
system clock
Clone Mode,
Tx Mode
(Tx/Rx = High)
Interleaved Tx data MSB = TxSYNC
Tx/Rx = tied high Optional buffered
Others = three-state
system clock
Clone Mode,
Rx Mode
(Tx/Rx = Low)
Rx_B data
Rx_A data
Tx/Rx = tied low
Optional buffered
system clock
IFACE3
Buffered Tx clock
Buffered Tx clock
Buffered Rx clock
Buffered Tx clock
Buffered Rx clock
Buffered Tx clock
Buffered Rx clock
Summary of Flexible I/O Modes
FD Mode
The following notes provide a general description of the FD
mode configuration. For more information, refer to Table 15.
The full-duplex (FD) mode can be configured by using mode
pins or with SPI programming. Using the SPI allows additional
configuration flexibility of the device.
Note the following about the Tx path in FD mode:
• Interpolation rate of 2× or 4× can be programmed with
mode pins or SPI.
FD mode is the only mode that supports full-duplex, receive,
and transmit concurrent operations. The upper 12-bit bus
(U12) is used to accept interleaved Tx data, and the lower 12-bit
bus (L12) is used to output interleaved Rx data. Either the Rx
path or the Tx path (or both) can be independently powered
• Max DAC update rate = 200 MSPS.
Max Tx input data rate = 80 MSPS/channel (160 MSPS
interleaved).
• TxSYNC is used to direct Tx input data.
down using either (or both) the RxPwrDwn and TxPwrDwn
TxSYNC = high indicates channel Tx_A data.
pins. FD mode requires interpolation of 2× or 4×.
TxSYNC = low indicates channel Tx_B data.
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