AD9775BSVZ Datasheet, PDF (24/56 Pages) Analog Devices – 14-Bit, 160 MSPS, 2×/4×/8× Interpolating Dual TxDAC+® Digital-to-Analog Converter

AD9775
DAC OPERATION
The dual, 14-bit DAC output of the AD9775, along with the
reference circuitry, gain, and offset registers, is shown in Figure 37.
Note that an external reference can be used by simply overdriving
the internal reference with the external reference. Referring to the
transfer functions in Equation 1, a reference current is set by the
internal 1.2 V reference, the external RSET resistor, and the values
in the coarse gain register. The fine gain DAC subtracts a small
amount from this and the result is input to IDAC and QDAC,
where it is scaled by an amount equal to 1024/24. Figure 38 and
Figure 39 show the scaling effect of the coarse and fine adjust
DACs. IDAC and QDAC are PMOS current source arrays,
segmented in a 5-4-5 configuration. The 5 MSBs control an array
of 31 current sources. The next four bits consist of 15 current
sources whose values are all equal to 1/16 of an MSB current
source. The 5 LSBs are binary weighted fractions of the middle
bits’ current sources. All current sources are switched to either
IOUTA or IOUTB, depending on the input code.
The fine adjustment of the gain of each channel allows for
improved balance of QAM modulated signals, resulting in
improved modulation accuracy and image rejection.
In the section Interfacing the AD9775 with the AD8345
Quadrature Modulator, the performance data shows to what
degree image rejection can be improved when the AD9775 is
used with an AD8345 quadrature modulator from Analog
Devices, Inc.
AVDD
84μA
REFIO
7kΩ
0.7V
25
20
2R MODE
15
10
1R MODE
5
0
0
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
0
5
10
15
20
COARSE GAIN REGISTER CODE
(ASSUMING RSET1, RSET2 = 1.9kΩ)
Figure 38. Coarse Gain Effect on IFULLSCALE
1R MODE
2R MODE
200
400
600
800
FINE GAIN REGISTER CODE
(ASSUMING RSET1, RSET2 = 1.9kΩ)
Figure 39. Fine Gain Effect on IFULLSCALE
1000
Figure 37. Equivalent Internal Reference Circuit
GAIN
CONTROL
REGISTERS
1.2VREF
REFIO
0.1μF
FINE
GAIN
DAC
OFFSET
CONTROL ^OFFSET
REGISTERS ^DAC
FINE
GAIN
DAC
IDAC
COARSE COARSE
GAIN
GAIN
DAC
DAC
QDAC
I_OUTA1
I_OUTB1
I_OUTA2
I_OUTB2
FSADJ1
RSET1
FSADJ2
RSET2
GAIN
OFFSET
CONTROL
REGISTERS
OFFSET
DAC
CONTROL
REGISTERS
Figure 40. DAC Outputs, Reference Current Scaling, and Gain/Offset Adjust
Rev. E | Page 24 of 56