AD9220_15 Datasheet, PDF (24/32 Pages) Analog Devices – Complete 12-Bit 1.5/3.0/10.0 MSPS Monolithic A/D Converters

AD9221/AD9223/AD9220
The offset calibration circuitry consists of a DAC, U5 and
the buffer amplifier, U4. The DAC is configured for a bipolar
adjustment span of ± 64 LSB with a 1/2 LSB resolution span
with respect to the AD9221/AD9223/AD9220. Note that both
current outputs of U5 were configured to provide a bipolar
adjustment span. Also, RC is used to decouple the output of
both DACs, U3 and U5, from their respective op amps.
The calibration procedure consists of a two step process. First,
the bipolar offset is calibrated by selecting CH2, the 2.5 V sys-
tem reference, of the analog multiplexer and preloading the DAC,
U5, with a midscale code of 1000 0000. If possible, several
readings of the A/D should be taken and averaged to determine
the required digital offset adjustment code, U5. This averaged
offset code requires an extra bit of resolution since 1 LSB of U5
equates to 1/2 LSB of the AD9221/AD9223/AD9220. The
required offset correction code to U5 can then be determined.
Second, the system gain is calibrated by selecting CH2, a 1.25 V
input that corresponds to –FS of the A/D. Before the value is
read, U4 should be preloaded with a code of 00 (Hex). Several
readings can also be taken and averaged to determine the digital
gain adjustment code to U2A. In this case, 1 LSB of the A/D
corresponds to 1 LSB of U4.
Due to the AD9221/AD9223/AD9220’s excellent INL perfor-
mance, a two-point calibration procedure (i.e., –FS to midscale)
instead of an endpoint calibration procedure was chosen. Also,
since the bipolar offset is insensitive to any gain adjustment (due
to the differential SHA of the A/D), an iterative calibration
process is not required. The temperature stability of the circuit
is enhanced by selecting a dual precision op amp for U2 (e.g.,
OP293) and low temperature drift, thin film resistors. Note that
this application circuit was not built at the release of this data
sheet. Please consult Analog Devices for application assistance
or comments.
0.1␮F
1.25V
1.25k⍀
U2B
2.5k⍀
2.5k⍀
0.1␮F
2.5k⍀ 162⍀
2.5k⍀
0.1␮F
U2A
1.25V
؎39mV
U1
1.1k⍀
REF43
CH1
0.1␮F 10␮F
2 ؋ 39⍀
+5V
CH2
2.5k⍀
R_C
CH3
100⍀
CH4
CH5
U6
ADG608
OUT
VREF(+)
VREF(–)
IOUT
U3
DAC08
CH6
CH7
2.5k⍀
IOUT
CH8
39⍀
U4
2.50V
39⍀
2.5k⍀
VREF(+)
VREF(–)
2.5k⍀
R_C
100⍀
IOUT
U5
DAC08
IOUT
R_C
100⍀
SENSE
VREF
AD9221/
AD9223/
AD9220
VINA
VINB
BIT 1 – BIT 12
OTR
Figure 35. Typical Multichannel Data Acquisition System
–24–
REV. E