AD5744_15 Datasheet, PDF (24/32 Pages) Analog Devices – Dual Low Power CMOS Analog Front End with DSP Microcomputer

AD5744
Preliminary Technical Data
DATA REGISTER
The data register is addressed by setting the three REG bits to 010. The DAC address bits select with which DAC channel the data transfer
is to take place (see Table 9). The data bits are in positions DB15 to DB2 as shown in Table 12.
Table 12. Programming the AD5744 Data Register
REG2
REG1
REG0
A2 A1 A0 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
1
0
DAC Address
14-Bit DAC Data
X
X
COARSE GAIN REGISTER
The coarse gain register is addressed by setting the three REG bits to 011. The DAC address bits select with which DAC channel the data
transfer is to take place (see Table 9). The coarse gain register is a 2-bit register and allows the user to select the output range of each DAC
as shown in Table 13 and Table 14.
Table 13. Programming the AD5744 Coarse Gain Register
REG2
REG1
REG0
A2
A1
A0
0
1
1
DAC Address
DB15 …. DB2
Don’t Care
DB1
DB0
CG1
CG0
Table 14. Output Range Selection
Output Range CG1 CG0
±10 V (default) 0 0
±10.2564 V
01
±10.5263 V
10
FINE GAIN REGISTER
The fine gain register is addressed by setting the three REG bits to 100. The DAC address bits select with which DAC channel the data
transfer is to take place (see Table 9). The fine gain register is a 6-bit register and allows the user to adjust the gain of each DAC channel
by −8 LSBs to +7.75 LSBs in 0.25 LSB steps as shown in Table 15 and Table 16. The adjustment is made to both the positive full-scale
points and the negative full-scale points simultaneously, each point being adjusted by ½ of one step. The fine gain register coding is twos
complement.
Table 15. Programming AD5744 Fine Gain Register
REG2 REG1 REG0 A2
A1
A0
1
0
0
DAC Address
DB15:DB6
Don’t Care
DB5 DB4 DB3 DB2 DB1 DB0
FG5 FG4 FG3 FG2 FG1 FG0
Table 16. AD5744 Fine Gain Register Options
Gain Adjustment
FG5
FG4
FG3
FG2
FG1
FG0
+7.75 LSBs
0
1
1
1
1
1
+7.5 LSBs
0
1
1
1
1
0
-
-
-
-
-
-
No Adjustment (default)
0
0
0
0
0
0
-
-
-
-
-
-
−7.75 LSBs
1
0
0
0
0
1
−8 LSBs
1
0
0
0
0
0
Rev. PrE | Page 24 of 32