ADT7519_15 Datasheet, PDF (23/44 Pages) Analog Devices – SPI-/IC-Compatible, Temperature Sensor, 4-Channel ADC and Quad Voltage Output

ADT7516/ADT7517/ADT7519
FUNCTIONAL DESCRIPTION—ANALOG INPUTS
Single-Ended Inputs
The ADT7516/ADT7517/ADT7519 offer four single-ended
analog input channels. The analog input range is from 0 V to
2.28 V, or 0 V to VDD. To maintain the linearity specification, it
is recommended that the maximum VDD value be set at 5 V.
Selection between the two input ranges is done by Bit C4 of the
Control Configuration 3 register (Address 0x1A). Setting this
bit to 0 sets up the analog input ADC reference to be sourced
from the internal voltage reference of 2.28 V. Setting the bit to 1
sets up the ADC reference to be sourced from VDD.
The ADC resolution is 10 bits and is mostly suitable for dc
input signals. Bits[C1:C2] of the Control Configuration 1
register (Address 0x18) are used to set up Pin 7 and Pin 8 as
AIN1 and AIN2. Figure 48 shows the overall view of the
4-channel analog input path.
M
AIN1
U
L
T
AIN2
I
P
AIN3
L
E
X
AIN4
E
R
10-BIT
ADC
TO ADC
VALUE
REGISTER
Figure 48. Quad Analog Input Path
Converter Operation
The analog input channels use a successive approximation ADC
based on a capacitor DAC. Figure 49 and Figure 50 show simpli-
fied schematics of the ADC. Figure 49 shows the ADC during
acquisition phase. SW2 is closed and SW1 is in Position A.
The comparator is held in a balanced condition and the
sampling capacitor acquires the signal on AIN.
INT V_REF
V_DD
SAMPLING
A ^CAPACITOR
AIN
SW1 _B
SW2
REF
CAP DAC
ACQUISITION
PHASE
REF/2
COMPARATOR
CONTROL
LOGIC
Figure 49. ADC Acquisition Phase
INT V_REF
V_DD
SAMPLING
A ^CAPACITOR
AIN
SW1 _B
SW2
REF
CAP DAC
CONVERSION
PHASE
REF/2
COMPARATOR
CONTROL
LOGIC
Figure 50. ADC Conversion Phase
When the ADC eventually goes into conversion phase (see
Figure 50), SW2 opens and SW1 moves to Position B, causing
the comparator to become unbalanced. The control logic and
the DAC are used to add and subtract fixed amounts of charge
from the sampling capacitor to bring the comparator back into
a balanced condition. When the comparator is rebalanced, the
conversion is complete. The control logic generates the ADC
output code. Figure 51 shows the ADC transfer function for the
analog inputs.
ADC TRANSFER FUNCTION
The output coding of the ADT7516/ADT7517/ADT7519 analog
inputs is straight binary. The designed code transitions occur
midway between successive integer LSB values (that is, 1/2 LSB,
3/2 LSB). The LSB is VDD/1024 or internal VREF/1024, internal
VREF = 2.28 V. The ideal transfer characteristic is shown in
Figure 51.
111...111
111...110
111...000
011...111
1LSB = INT V_REF/1024
1LSB = V_DD/1024
000...010
000...001
000...000
0V 1/2LSB
+V_REF – 1LSB
ANALOG INPUT
Figure 51. Single-Ended Transfer Function
To work out the voltage on any analog input channel, the
following method can be used:
1 LSB = reference (V)/1024
Convert value read back from AIN value register into decimal.
AIN voltage = AIN value (d) × LSB size
where d = decimal.
For example, if internal reference is used, VREF = 2.28 V.
AIN value = 512d
1 LSB size = 2.28 V/1024 = 2.226 × 10^−3
AIN voltage = 512 × 2.226 × 10^−3 = 1.14 V
Analog Input ESD Protection
Figure 52 shows the input structure on any of the analog input
pins that provide ESD protection. The diode provides the main
ESD protection for the analog inputs. Care must be taken that
the analog input signal never drops below the GND rail by
more than 200 mV. If this happens, the diode becomes forward-
biased and starts conducting current into the substrate. The
4 pF capacitor is the typical pin capacitance and the resistor is a
lumped component made up of the on resistance of the
multiplexer switch.
Rev. B | Page 23 of 44