AD9991 Datasheet, PDF (23/60 Pages) Analog Devices – 10-Bit CCD Signal Processor with Precision Timing Generator

MODE Register
The MODE register is a single register that selects the field tim-
ing of the AD9991. Typically, all of the field, V-sequence, and
V-pattern group information is programmed into the AD9991
at startup. During operation, the MODE register allows the user
to select any combination of field timing to meet the current
requirements of the system. The advantage of using the MODE
register in conjunction with preprogrammed timing is that it
greatly reduces the system programming requirements during
camera operation. Only a few register writes are required when
the camera operating mode is changed, rather than having to
write in all of the vertical timing information with each camera
mode change.
A basic still camera application might require five different
fields of vertical timing: one for draft mode operation, one for
autofocusing, and three for still image readout. All of the reg-
ister timing information for the five fields would be loaded at
AD9991
startup. Then, during camera operation, the MODE register
would select which field timing would be active, depending on
how the camera was being used.
Table X shows how the MODE register bits are used. The three
MSBs, D23–D21, are used to specify how many total fields will
be used. Any value from 1 to 7 can be selected using these three
bits. The remaining register bits are divided into 3-bit sections to
select which of the six fields are used and in which order. Up to
seven fields may be used in a single MODE write. The AD9991
will start with the Field timing specified by the first Field bits,
and on the next VD will switch to the timing specified by the
second Field bits, and so on.
After completing the total number of fields specified in Bits
D23 to D21, the AD9991 will repeat by starting at the first
Field again. This will continue until a new write to the MODE
register occurs. Figure 24 shows example MODE register set-
tings for different field configurations.
Table X. MODE Register Data Bit Breakdown (D23 = MSB)
D23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6
Total Number of 7th Field
Fields to Use.
0 = Field 0
1 = 1st Field Only 5 = Field 5
7 = All 7 Fields 6, 7 = Invalid
0 = Invalid
6th Field
0 = Field 0
5 = Field 5
6, 7 = Invalid
5th Field
0 = Field 0
5 = Field 5
6, 7 = Invalid
4th Field
0 = Field 0
5 = Field 5
6, 7 = Invalid
3rd Field
0 = Field 0
5 = Field 5
6, 7 = Invalid
5 4 3 2 1 D0
2nd Field
0 = Field 0
5 = Field 5
6, 7 = Invalid
1st Field
0 = Field 0
5 = Field 5
6, 7 = Invalid
EXAMPLE 1:
TOTAL FIELDS = 3, 1ST FIELD = FIELD 0, 2ND FIELD = FIELD 1, 3RD FIELD = FIELD 2
MODE REGISTER CONTENTS = 0x600088
FIELD 0
FIELD 1
FIELD 2
EXAMPLE 2:
TOTAL FIELDS = 2, 1ST FIELD = FIELD 3, 2ND FIELD = FIELD 4
MODE REGISTER CONTENTS = 0x400023
FIELD 3
FIELD 4
EXAMPLE 3:
TOTAL FIELDS = 4, 1ST FIELD = FIELD 5, 2ND FIELD = FIELD 1, 3RD FIELD = FIELD 4, 4TH FIELD = FIELD 2
MODE REGISTER CONTENTS = 0x80050D
FIELD 5
FIELD 1
FIELD 4
FIELD 2
Figure 24. Using the MODE Register to Select Field Timing
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