AD9952_15 Datasheet, PDF (23/28 Pages) Analog Devices – 400 MSPS 14-Bit, 1.8 V CMOS Direct Digital Synthesizer

When in LSB-first mode, the device reads the instruction byte
first (LSB to MSB), then calculates the expected number of
bytes from the address provided, and then receives/provides
data from the referenced register in LSB-first format (LSB to
MSB of the register selected).
Example Operation
In this example, the amplitude scale factor is calculated and
written to present a 45° phase offset on the output of the
AD9952. First, the default MSB-first case is considered. Then,
the alternate LSB-first method is presented. For the purpose of
the example, the following assumptions are made:
• The microcontroller is currently meeting the setup and
hold times for the serial I/O port (this is a software only
example).
• The phase offset change needs to occur at a known point
in time (the data transfer needs to be synchronous).
• No other values are written or altered during the example.
MSB-First Mode (Default) Case
First, the phase offset word (POW) needs to be calculated. Per
the formula in the Phase Offset Word (POW) section, the POW
is calculated to be 45/360 × 2¹⁴ or 2048 (h’800).
Next, the instruction byte to write to the POW needs to be sent.
The first bit is 0, to indicate a write. The next two bits are don’t
care bits, and are set to 0. The last 5 bits correspond to the POW
address, which is h’05. This makes the instruction byte:
b’00001001.
Next, the data calculated in Step 1 is sent to the part. The POW
is 2 bytes wide. To make the 14-bit value fit into the 16-bit
register, the 2 MSBs are padded with don’t care bits. In this
example, the don’t care bits are assumed to be 0. The 2 data
bytes therefore are b’00001000 00000000.
Once the 24 bits of data are sent to the part (8 bits of instruction
byte and 16 bits of data), the phase offset word I/O buffer is
changed, but the change has not been made in the phase offset
word (POW) register. As no other data is being written in this
example, the I/O update pulse, which is 1.5 SYNC_CLK cycles
in duration, is sent to the I/O update pin. This transfers the data
from the POW I/O buffer to the POW register.
LSB First Mode Case
The values calculated in the MSB-first mode case are still valid.
The order of the bits in the instruction byte and in the data
bytes for the POW need to be reversed.
First, the instruction byte is sent. Because the part is now in
LSB-first mode, the value sent is b’10010000.
Next, the data bytes are sent in LSB-first mode: b’00000000
00010000.
AD9952
Finally, as before, the I/O update pin is pulsed with a high signal
for duration of 1.5 SYNC_CLK cycles, to transfer the contents
of the POW I/O buffer to the POW register.
POWER-DOWN FUNCTIONS
The AD9952 supports an externally controlled or hardware
power-down feature as well as the more common software
programmable power-down features found in other Analog
Devices DDS products.
The software control power-down allows the DAC, comparator,
PLL, input clock circuitry, and digital logic to be individually
powered down via unique control bits (CFR1 [7:4]). With the
exception of CFR1 [6], these bits are not active when the
externally controlled power-down pin (PWRDWNCTL) is high.
External power-down control is supported on the AD9952 via
the PWRDWNCTL input pin.
When the PWRDWNCTL input pin is high, the AD9952 enters
a power-down mode based on the CFR1 [3] bit. When the
PWRDWNCTL input pin is low, the external power-down
control is inactive.
When the CFR1 [3] bit is 0 and the PWRDWNCTL input pin is
high, the AD9952 is put into a fast recovery power-down mode.
In this mode, the digital logic and the DAC digital logic are
powered down. The DAC bias circuitry, comparator, PLL,
oscillator, and clock input circuitry is not powered down. The
comparator can be individually powered down by setting the
comparator power-down bit, CFR1 [6] = 1.
When the CFR1 [3] bit is high, and the PWRDWNCTL input
pin is high, the AD9952 is put into the full power-down mode.
In this mode, all functions are powered down. This includes the
DAC and PLL, which take a significant amount of time to
power up.
When the PWRDWNCTL input pin is high, the individual
power-down bits (CFR1 [7] and CFR1 [5:4]) are invalid (don’t
care) and unused. When the PWRDWNCTL input pin is low, the
individual power-down bits control the power-down modes of
operation.
Note that the power-down signals are all designed such that a
Logic 1 indicates the low power mode and a Logic 0 indicates
the active or power-up mode.
Table 7 indicates the logic level for each power-down bit that
drives out of the AD9952 core logic to the analog section and
the digital clock generation section of the chip for the external
power-down operation.
Rev. B | Page 23 of 28