AD9891 Datasheet, PDF (23/58 Pages) Analog Devices – CCD Signal Processors with Precision Timing™ Generator

HD
VSG1–
VSGX
V1
V2
V3
V4
VD
HD
V1–V4
SENSOR GATE LINE
AD9891/AD9895
2ND GROUP OF V-SEQUENCES ARE OUTPUT DURING VSG LINE
Figure 25. Example of Second Sequences During Sensor Gate Line
LINE 0
LINE 1
LINE 2
LINE 24
LINE 25
REGION AREA 0
REGION AREA 1: SWEEP REGION
Figure 26. Example of Sweep Region for High Speed Vertical Shift
REGION AREA 2
REV. A
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