AD9857_04 Datasheet, PDF (23/40 Pages) Analog Devices – CMOS 200 MSPS 14-Bit Quadrature Digital Upconverter

The output compliance voltage of the AD9857 is −0.5 V to
+1.0 V. Any signal developed at the DAC output should not
exceed 1.0 V, otherwise, signal distortion results. Furthermore,
the signal may extend below ground as much as 0.5 V without
damage or signal distortion. The use of a transformer with a
grounded center tap for common-mode rejection results in
signals at the AD9857 DAC output pins that are symmetrical
about ground.
As previously mentioned, by differentially combining the two
signals, the user can provide some degree of common-mode
signal rejection. A differential combiner might consist of a
transformer or an op amp. The object is to combine or amplify
only the difference between two signals and to reject any
common, usually undesirable, characteristic, such as 60 Hz
AD9857
hum or clock feed-through that is equally present on both input
signals. The AD9857 true and complement outputs can be
differentially combined using a broadband 1:1 transformer with
a grounded, center-tapped primary to perform differential
combining of the two DAC outputs.
REFERENCE CLOCK MULTIPLIER
It is often difficult to provide a high quality oscillator with an
output in the frequency range of 100 MHz – 200 MHz. The
AD9857 allows the use of a lower-frequency oscillator that can
be multiplied to a higher frequency by the on-board reference
clock multiplier, implemented with a phase locked loop
architecture. See the Ease of Use Features section for a more
thorough discussion of the reference clock multiplier feature.
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