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AD9253 Datasheet, PDF (23/40 Pages) Analog Devices – Quad, 14-Bit, 80 MSPS/105 MSPS/125 MSPS
Data Sheet
AD9253
Differential Input Configurations
There are several ways to drive the AD9253 either actively or
passively. However, optimum performance is achieved by driving
the analog inputs differentially. Using a differential double balun
configuration to drive the AD9253 provides excellent performance
and a flexible interface to the ADC (see Figure 58) for baseband
applications.
For applications where SNR is a key parameter, differential trans-
former coupling is the recommended input configuration (see
Figure 59), because the noise performance of most amplifiers is
not adequate to achieve the true performance of the AD9253.
Regardless of the configuration, the value of the shunt capacitor,
C, is dependent on the input frequency and may need to be
reduced or removed.
It is not recommended to drive the AD9253 inputs single-ended.
VOLTAGE REFERENCE
A stable and accurate 1.0 V voltage reference is built into the
AD9253. VREF can be configured using either the internal 1.0 V
reference or an externally applied 1.0 V reference voltage. The
various reference modes are summarized in the Internal Reference
Connection section and the External Reference Operation
section. The VREF pin should be externally decoupled to
ground with a low ESR, 1.0 μF capacitor in parallel with a low
ESR, 0.1 μF ceramic capacitor.
Internal Reference Connection
A comparator within the AD9253 detects the potential at the
SENSE pin and configures the reference into two possible
modes, which are summarized in Table 9. If SENSE is grounded,
the reference amplifier switch is connected to the internal resistor
divider (see Figure 57), setting VREF to 1.0 V.
Table 9. Reference Configuration Summary
Selected Mode
Fixed Internal
Reference
Fixed External
Reference
SENSE
Voltage (V)
AGND to
0.2
AVDD
Resulting
VREF (V)
1.0 internal
1.0 applied
to external
VREF pin
Resulting
Differential
Span (V p-p)
2.0
2.0
VIN+A/VIN+B
VIN–A/VIN–B
ADC
CORE
1.0µF
VREF
0.1µF
SENSE
SELECT
LOGIC
0.5V
ADC
Figure 57. Internal Reference Configuration
0.1µF
2V p-p
ET1-1-I3
0.1µF
C
33Ω
33Ω
0.1µF
C
R *C1
33Ω
C 5pF
R
33Ω *C1
R
VIN+x
ADC
VIN–x
VCM
0.1µF
200Ω
C 0.1µF
*C1 IS OPTIONAL
Figure 58. Differential Double Balun Input Configuration for Baseband Applications
2V p-p
ADT1-1WT
1:1 Z RATIO R *C1
49.9Ω
33Ω
C
5pF
R
33Ω
*C1
VIN+x
ADC
VIN–x VCM
200Ω
0.1μF
0.1µF
*C1 IS OPTIONAL
Figure 59. Differential Transformer-Coupled Configuration
for Baseband Applications
Rev. 0 | Page 23 of 40