AD7766_15 Datasheet, PDF (23/25 Pages) Analog Devices – 24-Bit, 8.5 mW, 109 dB, 128 kSPS/64 kSPS/32 kSPS ADCs

AD7766
V_REF+ INPUT SIGNAL
The AD7766/AD7766-1/AD7766-2 VREF + pin is supplied with a
voltage in the range of 2.4 V to 2 × AVDD (nominally 5 V). It is
recommended that the VREF+ input be generated by a low noise
voltage reference. Examples of such references are the ADR445,
ADR435, ADR425 (5 V output), and ADR421 (2.5 V output).
Typical reference supply circuits are shown in Figure 46.
The reference voltage input pin (VREF+) also acts as a power
supply to the AD7766/AD7766-1/AD7766-2 devices. For a 5 V
VREF+ input, a full-scale input of 5 V on both VIN+ and VIN− can
be applied while voltage supplies to pins AVDD remain at 2.5 V.
This configuration reduces the number of different supplies
required.
The output of the low noise voltage reference does not require a
buffer; however, decoupling the output of the low noise reference is
important. Place a 0.1 μF capacitor at the output of the voltage
reference devices (ADR445, ADR435, ADR425, and ADR421)
and follow the decoupling advice provided for the reference
device chosen.
As mentioned, the nominal supply to the VREF+ pin is 5 V to
achieve the full dynamic range available. When a 2.5 V VREF+
input is used (that is, in low power applications), the signal-to-
noise ratio and dynamic range figures (generated using a 5 V
VREF+ input) quoted in the Specifications section decrease by
6 dB, a direct result of halving the available input range.
The AD7766/AD7766-1/AD7766-2 devices require a 100 μF
capacitor to ground, which acts as a decoupling capacitor and as
a reservoir of charge for the VREF+ pin. Place this capacitor as
close to the AD7766/AD7766-1/AD7766-2 devices as possible.
Reducing the value of this capacitor (C40 in Figure 46) to 10 μF
typically degrades noise performance by 1 dB. C40 can be an
electrolytic or tantalum capacitor.
REFERENCE
SUPPLY
V+
C34
10µF
V_IN
V_OUT
C35
0.1µF
ADR4xx
C39
0.1µF
V_REF+
C40
100µF
AD7766/
AD7766-1/
AD7766-2
Figure 46. AD7766/AD7766-1/AD7766-2 Reference Input Configuration
MULTIPLEXING ANALOG INPUT CHANNELS
The AD7766/AD7766-1/AD7766-2 can be used with a multi-
plexer configuration. As per any converter that uses a digital
filtering block, the maximum switching rate or the output data
rate per channel is a function of the digital filter settling time.
A user multiplexing the analog inputs to a converter that
employs a digital filter must wait the full digital filter settling
time before a valid conversion result can be achieved; after this
settling time, the channel can be switched. Then, the full
settling time must again be observed before a valid conversion
result is available and the input is switched once more.
The AD7766 filter settling time equals 74 divided by the output
data rate in use. The maximum switching frequency in a multi-
plexed application is, therefore, 1/(74/ODR), where the output
data rate (ODR) is a function of the applied MCLK frequency
and the decimation rate employed by the device in question. For
example, applying a 1.024 MHz MCLK frequency to the AD7766
results in a maximum output data rate of 128 kHz, which in
turn allows a 1.729 kHz multiplexer switching rate.
The AD7766-1 and the AD7766-2 employ digital filters with
longer settling time to achieve greater precision; thus, the
maximum switching frequency for these devices is 864 Hz and
432 Hz, respectively.
Rev. C | Page 22 of 24