AD7714YRZ Datasheet, PDF (23/40 Pages) Analog Devices – 3 V/5 V, CMOS,500 mA Signal Conditioning ADC

AD7714
ANALOG FILTERING
value which, when normalized, is subtracted from all conversion
The digital filter does not provide any rejection at integer mul-
results. The full-scale calibration register contains a value
tiples of the input sampling frequency, as outlined earlier. How- _{which, when normalized, is multiplied by all conversion results.}
ever, due to the AD7714’s high oversampling ratio, these bands _{The offset calibration coefficient is subtracted from the result}
occupy only a small fraction of the spectrum and most broad-
prior to the multiplication by the full-scale coefficient. This
band noise is filtered. This means that the analog filtering re-
means that the full-scale coefficient is effectively a span or gain
quirements in front of the AD7714 are considerably reduced
coefficient.
versus a conventional converter with no on-chip filtering. In
addition, because the part’s common-mode rejection perfor-
The AD7714 offers self-calibration, system calibration and
2
mance of 100␣ dB extends out to several kHz, common-mode
background calibration facilities. For full calibration to occur
noise in this frequency range will be substantially reduced.
on the selected channel, the on-chip microcontroller must record
the modulator output for two different input conditions. These
Depending on the application, however, it may be necessary to
are “zero-scale” and “full-scale” points. These points are de-
provide attenuation prior to the AD7714 in order to eliminate
rived by performing a conversion on the different input voltages
unwanted frequencies from these bands which the digital filter
provided to the input of the modulator during calibration. As a
will pass. It may also be necessary in some applications to pro-
result, the accuracy of the calibration can only be as good as the
vide analog filtering in front of the AD7714 to ensure that dif-
noise level which the part provides in normal mode. The result
ferential noise signals outside the band of interest do not
of the “zero-scale” calibration conversion is stored in the Zero
saturate the analog modulator.
Scale Calibration Register for the appropriate channel. The
If passive components are placed in front of the AD7714, in
result of the “full-scale” calibration conversion is stored in the
unbuffered mode, care must be taken to ensure that the source Full-Scale Calibration Register for the appropriate channel. With
impedance is low enough so as not to introduce gain errors in
these readings, the microcontroller can calculate the offset and
the system. This significantly limits the amount of passive anti- the gain slope for the input to output transfer function of the
aliasing filtering which can be provided in front of the AD7714 converter. Internally, the part works with 33 bits of resolution
when it is used in unbuffered mode. However, when the part is to determine its conversion result of either 16 bits or 24 bits.
used in buffered mode, large source impedances will simply
result in a small dc offset error (a 10␣ kΩ source resistance will
cause an offset error of less than 10␣ µV). Therefore, if the sys-
tem requires any significant source impedances to provide pas-
sive analog filtering in front of the AD7714, it is recommended
that the part be operated in buffered mode.
Self-Calibration
A self-calibration is initiated on the AD7714 by writing the
appropriate values (0, 0, 1) to the MD2, MD1 and MD0 bits of
the Mode Register. In the self-calibration mode with a unipolar
input range, the zero-scale point used in determining the cali-
bration coefficients is with the inputs of the differential pair
CALIBRATION
The AD7714 provides a number of calibration options which
can be programmed via the MD2, MD1 and MD0 bits of the
Mode Register. The different calibration options are outlined
in the Mode Register and Calibration Sequences sections. A
calibration cycle may be initiated at any time by writing to these
bits of the Mode Register. Calibration on the AD7714 removes
offset and gain errors from the device. A calibration routine
should be initiated on the device whenever there is a change in
the ambient operating temperature or supply voltage. It should
also be initiated if there is a change in the selected gain, filter
notch or bipolar/unipolar input range.
The AD7714 gives the user access to the on-chip calibration
registers allowing the microprocessor to read the device’s cali-
bration coefficients and also to write its own calibration coeffi-
cients to the part from prestored values in E²PROM. This gives
the microprocessor much greater control over the AD7714’s
calibration procedure. It also means that the user can verify
that the device has performed its calibration correctly by com-
paring the coefficients after calibration with prestored values in
E²PROM. The values in these calibration registers are 24-bit
wide. In addition, the span and offset for the part can be
adjusted by the user.
internally shorted on the part (i.e., AIN(+) = AIN(–) = Internal
Bias Voltage). The PGA is set for the selected gain (as per G2,
G1, G0 bits in the Mode Register) for this zero-scale calibration
conversion. The full-scale calibration conversion is performed at
the selected gain on an internally-generated voltage of V_REF/
Selected Gain.
The duration time of the calibration is 6 × 1/Output Rate. This
is made up of 3 × 1/Output Rate for the zero-scale calibration
and 3 × 1/Output Rate for the full-scale calibration. At this time
the MD2, MD1 and MD0 bits in the Mode Register return to
0, 0, 0. This gives the earliest indication that the calibration
sequence is complete. The DRDY line goes high when calibra-
tion is initiated and does not return low until there is a valid
new word in the data register. The duration time from the cali-
bration command being issued to DRDY going low is 9 × 1/
Output Rate. This is made up of 3 × 1/Output Rate for the zero-
scale calibration, 3 × 1/Output Rate for the full-scale calibration
and 3 × 1/Output Rate for a conversion on the analog input. If
DRDY is low before (or goes low during) the calibration com-
mand write to the Mode Register, it may take up to one modu-
lator cycle (MCLK␣ IN/128) before DRDY goes high to indicate
that calibration is in progress. Therefore, DRDY should be
ignored for up to one modulator cycle after the last bit of the
calibration command is written to the Mode Register.
There is a significant variation in the value of these coefficients
across the different output update rates, gains and unipolar/
bipolar operation. Internally in the AD7714, these coefficients
are normalized before being used to scale the words coming out
of the digital filter. The offset calibration register contains a
For bipolar input ranges in the self-calibrating mode, the se-
quence is very similar to that just outlined. In this case, the two
points are exactly the same as above but since the part is config-
ured for bipolar operation, the output code for zero differential
input is 800000 Hex in 24-bit mode.
REV. C
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