AD7366_15 Datasheet, PDF (23/29 Pages) Analog Devices – True Bipolar Input, Dual 12-Bit/14-Bit, 2-Channel, Simultaneous Sampling SAR ADC

AD7366/AD7367
SERIAL INTERFACE
Figure 25 and Figure 26 show the detailed timing diagram for
serial interfacing to the AD7366 and the AD7367. On the
falling edge of CNVST, the AD7366/AD7367 simultaneously
convert the selected channels. These conversions are performed
using the on-chip oscillator. After the falling edge of CNVST,
the BUSY signal goes high, indicating that the conversion has
started. The BUSY signal returns low when the conversion has
been completed. The data can now be read from the D_OUT pins.
The CS and SCLK signals are required to transfer data from the
AD7366/AD7367. The AD7366/AD7367 have two output pins
corresponding to each ADC. Data can be read from the AD7366/
AD7367 using both D_OUTA and D_OUTB. Alternatively, a single
output pin of the user’s choice can be used. The SCLK input
signal provides the clock source for the serial interface. The CS
goes low to access data from the AD7366/AD7367. The falling
edge of CS takes the bus out of three-state and clocks out the
MSB of the conversion result. The data stream consists of
12 bits of data for the AD7366 and 14 bits of data for the
AD7367, MSB first. The first bit of the conversion result is
valid on the first SCLK falling edge after the CS falling edge.
The subsequent 11/13 bits of data for the AD7366/AD7367,
respectively, are clocked out on the falling edge of the SCLK
signal. A minimum of 12 clock pulses must be provided to the
AD7366 to access each conversion result, and a minimum of
14 clock pulses must be provided to the AD7367 to access the
conversion result. Figure 25 shows how a 12 SCLK read is used
to access the conversion results for the AD7366, and Figure 26
illustrates the case for the AD7367 with a 14 SCLK read.
On the rising edge of CS the conversion is terminated and
D_OUTA and D_OUTB return to three-state. If CS is not brought
high, but is instead held low for an additional 14 SCLK cycles
the data from the other DOUT pin follows on the selected
DOUT pin. Note, the second serial result from the AD7366 is
preceeded by two zeros. See Figure 27 and Figure 28, where
D_OUTA is shown. In this case, the D_OUT line in use returns to
three-state on the rising edge of CS.
If the falling edge of SCLK coincides with the falling edge of CS,
the falling edge of SCLK is not acknowledged by the AD7366/
AD7367, and the next falling edge of SCLK is the first one
registered after the falling edge of CS.
The CS pin can be brought low before the BUSY signal goes
low, indicating the end of a conversion. When CS is at a logic
low state, the data bus is brought out of three-state. This feature
can be used to ensure that the MSB is valid on the falling edge
of BUSY by bringing CS low a minimum of t₄ before the BUSY
signal goes low. The dotted CS line in Figure 22 and Figure 23
illustrates this feature.
Alternatively, the CS pin can be tied to a low logic state continu-
ously. In this case, the D_OUT pins never enter three-state and the
data bus is continuously active. Under these conditions, the MSB
of the conversion result for the AD7366/AD7367 is available on
the falling edge of the BUSY signal. The next most significant
bit is available on the first SCLK falling edge after the BUSY
signal has gone low. This mode of operation enables the user to
read the MSB as soon as it is made available by the converter.
CS
SCLK
1
2
D_OUTA
D_OUTB
THREE-
STATE
t₄
DB10
DB11
DB9
t₈
3
4
5
t₅
t₆
DB8
t₇
DB2
DB1
Figure 25. Serial Interface Timing Diagram for the AD7366
12
t₉
DB0
THREE-STATE
CS
SCLK
1
2
D_OUTA
D_OUTB _THREE-
STATE
t₄
DB12
DB13
DB11
t₈
3
4
5
t₅
t₆
DB10
t₇
DB2
DB1
Figure 26. Serial Interface Timing Diagram for the AD7367
14
t₉
DB0
THREE-STATE
Rev. D | Page 22 of 28