AD73411_15 Datasheet, PDF (23/36 Pages) Analog Devices – Low-Power Analog Front End with DSP Microcomputer

AD73411
Terminating Unused Pin
The following chart shows the recommendations for terminating
unused pins.
Pin Terminations
Pin
Name
I/O
Hi-Z*
3-State Reset Caused
(Z)
State By
Unused
Configuration
XTAL
CLKOUT
A13:1 or
IAD12:0
A0
D23:8
D7 or
IWR
D6 or
IRD
D5 or
IAL
D4 or
IS
D3 or
IACK
D2:0 or
IAD15:13
PMS
DMS
BMS
IOMS
CMS
RD
WR
BR
BG
BGH
IRQ2/PF7
I
O
O (Z)
I/O (Z)
O (Z)
I/O (Z)
I/O (Z)
I
I/O (Z)
I
I/O (Z)
I
I/O (Z)
I
I/O (Z)
I/O (Z)
I/O (Z)
O (Z)
O (Z)
O (Z)
O (Z)
O (Z)
O (Z)
O (Z)
I
O (Z)
O
I/O (Z)
I
O
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
I
Hi-Z
I
Hi-Z
I
Hi-Z
I
Hi-Z
Hi-Z
Hi-Z
O
O
O
O
O
O
O
I
O
O
I
IRQL1/PF6 I/O (Z) I
IRQL0/PF5 I/O (Z) I
IRQE/PF4 I/O (Z) I
SCLK0 I/O
I
RFS0
I/O
I
DR0
I
I
TFS0
I/O
O
DT0
O
O
SCLK1 I/O
I
RFS1/IRQ0 I/O
I
DR1/FI I
I
TFS1/IRQ1 I/O
O
DT1/FO O
O
EE
I
I
EBR
I
I
EBG
O
O
ERESET I
I
EMS
O
O
EINT
I
I
ECLK
I
I
ELIN
I
I
ELOUT O
O
BR, EBR
IS
BR, EBR
BR, EBR
BR, EBR
BR, EBR
BR, EBR
BR, EBR
BR, EBR
BR, EBR
IS
BR, EBR
BR, EBR
BR, EBR
BR, EBR
BR, EBR
BR, EBR
BR, EBR
EE
Float
Float
Float
Float
Float
Float
Float
High (Inactive)
Float
High (Inactive)
Float
Low (Inactive)
Float
High (Inactive)
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
High (Inactive)
Float
Float
Input = High (Inactive)
or Program as Output,
Set to 1, Let Float
Input = High (Inactive)
or Program as Output,
Set to 1, Let Float
Input = High (Inactive)
or Program as Output,
Set to 1, Let Float
Input = High (Inactive)
or Program as Output,
Set to 1, Let Float
Input = High or Low,
Output = Float
High or Low
High or Low
High or Low
Float
Input = High or Low,
Output = Float
High or Low
High or Low
High or Low
Float
NOTES
*Hi-Z = High Impedance.
1. If the CLKOUT pin is not used, turn it OFF.
2. If the Interrupt/Programmable Flag pins are not used, there are two options:
Option 1: When these pins are configured as INPUTS at reset and function
as interrupts and input flag pins, pull the pins High (inactive).
Option 2: Program the unused pins as OUTPUTS, set them to 1, and let
them float.
3. All bidirectional pins have three-stated outputs. When the pins is configured
as an output, the output is Hi-Z (high impedance) when inactive.
4. CLKIN, RESET, and PF3:0 are not included in the table because these pins
must be used.
Interrupts
The interrupt controller allows the processor to respond to the
eleven possible interrupts and RESET with minimum overhead.
The AD73411 provides four dedicated external interrupt
input pins, IRQ2, IRQL0, IRQL1, and IRQE. In addition,
SPORT1 may be reconfigured for IRQ0, IRQ1, FLAG_IN,
and FLAG_OUT, for a total of six external interrupts. The
AD73411 also supports internal interrupts from the timer, the
byte DMA port, the two serial ports, software, and the power-
down control circuit. The interrupt levels are internally prioritized
and individually maskable (except power-down and reset). The
IRQ2, IRQ0, and IRQ1 input pins can be programmed to be
either level- or edge-sensitive. IRQL0 and IRQL1 are level-
sensitive and IRQE is edge-sensitive. The priorities and vector
addresses of all interrupts are shown in Table XVII.
Table XVII. Interrupt Priority and Interrupt Vector Addresses
Interrupt Vector
Source of Interrupt
Address (Hex)
RESET (or Power-Up with PUCR = 1) 0000 (Highest Priority)
Power-Down (Nonmaskable)
IRQ2
IRQL1
IRQL0
002C
0004
0008
000C
SPORT0 Transmit
0010
SPORT0 Receive
IRQE
0014
0018
BDMA Interrupt
SPORT1 Transmit or IRQ1
SPORT1 Receive or IRQ0
001C
0020
0024
Timer
0028 (Lowest Priority)
Interrupt routines can either be nested, with higher priority
interrupts taking precedence, or processed sequentially. Interrupts
can be masked or unmasked with the IMASK register. Individual
interrupt requests are logically ANDed with the bits in IMASK;
the highest priority unmasked interrupt is then selected. The
power-down interrupt is nonmaskable.
The AD73411 masks all interrupts for one instruction cycle
following the execution of an instruction that modifies the
IMASK register. This does not affect serial port autobuffering
or DMA transfers.
The interrupt control register, ICNTL, controls interrupt nest-
ing and defines the IRQ0, IRQ1, and IRQ2 external interrupts
to be either edge- or level-sensitive. The IRQE pin is an external
edge-sensitive interrupt and can be forced and cleared. The
IRQL0 and IRQL1 pins are external level-sensitive interrupts.
The IFC register is a write-only register used to force and clear
interrupts. On-chip stacks preserve the processor status and are
automatically maintained during interrupt handling. The stacks
REV. 0
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