AD9952YSVZ Datasheet, PDF (22/28 Pages) Analog Devices – 400 MSPS 14-Bit, 1.8 V CMOS Direct Digital Synthesizer

AD9952
SYSCLK
SYNC_CLK
A
B
A
B
I/O UPDATE
DATA IN
I/O BUFFERS
DATA IN
REGISTERS
DATA 1
DATA 0
DATA 2
DATA 1
DATA 3
DATA 2
THE DEVICE REGISTERS AN I/O UPDATE AT POINT A. THE DATA IS TRANSFERRED FROM THE I/O BUFFERS AT POINT B.
Figure 26. Timing of I/O Update Signal vs. Actual Register Update
Serial Interface Port Pin Description
CS
SCLK—Serial Clock. The serial clock pin is used to synchronize
●●●
data to and from the AD9952 and to run the internal state
machines. SCLK maximum frequency is 25 MHz.
SCLK
●●●
CS—Chip Select Bar. CS is active low input that allows more
than one device on the same serial communication line. The
SDO pin and SDIO pin go to a high impedance state when this
input is high. If driven high during any communication cycle,
the cycle is suspended until CS is reactivated low. Chip select
can be tied low in systems that maintain control of SCLK.
When toggling CS, it is important that care is taken to meet the
clock setup time with respect to the falling edge of CS and TCSU
(see Figure 27).
SDIO—Serial Data I/O. Data is always written into the AD9952
on this pin. However, this pin can be used as a bidirectional
data line. Bit 9 of Register 0x00 controls the configuration of
this pin. The default is Logic 0, which configures the SDIO pin
as bidirectional. In order to guarantee proper serial I/O port
operation (see Figure 27), data on this pin must be set up and held
to the rising edge of SCLK on read operations.
SDO—Serial Data Out. Data is read from this pin for protocols
that use separate lines for transmitting and receiving data. In
the case where the AD9952 operates in a single bidirectional
I/O mode, this pin does not output data and is set to a high
impedance state.
IOSYNC—Synchronizes the I/O port state machines without
affecting the registers’ contents. An active high input on the
IOSYNC pin causes the current communication cycle to abort.
After IOSYNC returns low (Logic 0), another communication
cycle can begin, starting with the instruction byte write.
SDIO
●●●
TCSU
TDSU
TDH
TDH
DVDD I/O = 3.3V
TCSU = 3ns
TDSU = 3ns
TDH = 0ns
DVDD I/O = 1.8V
TCSU = 5ns
TDSU = 5ns
TDH = 0ns
Figure 27. Serial Port I/O Setup (TCSU, TDSU) and Hold (TDH) Times
SCLK
SDIO
SDO
TDV = 25ns
Figure 28. Serial Port I/O Data Valid Time (TDV) During Readback
MSB/LSB Transfers
The AD9952 serial port can support both most significant bit
(MSB) first or least significant bit (LSB) first data formats. The
control register, Register 0x00, Bit 8, controls this functionality.
The default value of Register 0x00 [8] is low (MSB first).
When the control register (0x00 [8]) is set high, the AD9952
serial port is in LSB-first format. The instruction byte must be
written in the format indicated by the control register (0x00
[8]), and the instruction byte must be written from least
significant bit to most significant bit (right to left in the table
located in the Instruction Byte Details section).
Note that even in LSB-first mode, the two respective phases of
the communication cycle, the instruction byte phase and the
data communication phase, retain their respective positions.
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