AD9861 Datasheet, PDF (22/52 Pages) Analog Devices – Mixed-Signal Front-End (MxFE-TM) Baseband Transceiver for Broadband Applications

AD9861
THEORY OF OPERATION
SYSTEM BLOCK
The AD9861 is targeted to cover the mixed-signal front end
needs of multiple wireless communication systems. It features a
receive path that consists of dual 10-bit receive ADCs, and a
transmit path that consists of dual 10-bit transmit DACs
(TxDAC). The AD9861 integrates additional functionality
typically required in most systems, such as power scalability,
additional auxiliary converters, Tx gain control, and clock
multiplication circuitry.
The AD9861 minimizes both size and power consumption to
address the needs of a range of applications from the low power
portable market to the high performance base station market.
The part is provided in a 64-lead lead frame chip scale package
(LFCSP) that has a footprint of only 9 mm × 9 mm. Power
consumption can be optimized to suit the particular application
beyond just a speed grade option by incorporating power-down
controls, low power ADC modes, TxDAC power scaling, and a
half-duplex mode, which automatically disables the unused
digital path.
The AD9861 uses two 10-bit buses to transfer Rx path data and
Tx path data. These two buses support 20-bit parallel data
transfers or 10-bit interleaved data transfers. The bus is
configurable through either external mode pins or through
internal registers settings. The registers allow many more
options for configuring the entire device.
The following sections discuss the various blocks of the AD9861:
Rx block, Tx block, the auxiliary converters, the digital block,
programmable registers and the clock distribution block.
Rx PATH BLOCK
Rx Path General Description
The AD9861 Rx path consists of two 10-bit, 50 MSPS (for the
AD9861-50) or 80 MSPS (for the AD9861-80) analog-to-digital
converters (ADCs). The dual ADC paths share the same
clocking and reference circuitry to provide optimal matching
characteristics. Each of the ADCs consists of a 9-stage differen-
tial pipelined switched capacitor architecture with output error
correction logic.
The pipelined architecture permits the first stage to operate on a
new input sample, while the remaining stages operate on
preceding samples. Sampling occurs on the falling edge of the
input clock. Each stage of the pipeline, excluding the last,
consists of a low resolution flash ADC and a residual multiplier
to drive the next stage of the pipeline. The residual multiplier
uses the flash ADC output to control a switched capacitor
digital-to-analog converter (DAC) of the same resolution. The
DAC output is subtracted from the stage’s input signal, and the
residual is amplified (multiplied) to drive the next pipeline
stage. The residual multiplier stage is also called a multiplying
DAC (MDAC). One bit of redundancy is used in each one of
the stages to facilitate digital correction of flash errors. The last
stage simply consists of a flash ADC.
The differential input stage is dc self-biased and allows
differential or single-ended inputs. The output-staging block
aligns the data, carries out the error correction, and passes the
data to the output buffers.
The latency of the Rx path is about 5 clock cycles.
Rx Path Analog Input Equivalent Circuit
The Rx path analog inputs of the AD9861 incorporate a novel
structure that merges the function of the input sample-and-
hold amplifiers (SHAs) and the first pipeline residue amplifiers
into a single, compact switched capacitor circuit. This structure
achieves considerable noise and power savings over a conven-
tional implementation that uses separate amplifiers by eliminating
one amplifier in the pipeline.
Figure 70 illustrates the equivalent analog inputs of the AD9861
(a switched capacitor input). Bringing CLK to logic high opens
switch S3 and closes switches S1 and S2; this is the sample mode
of the input circuit. The input source connected to VIN+ and
VIN− must charge capacitor CH during this time. Bringing CLK
to a logic low opens S2, and then switch S1 opens followed by
closing S3. This puts the input circuit into hold mode.
VIN+
VIN–
S1
R_IN
C_IN
V_CM
R_IN
C_IN
C_H
+
S3
C_H
S2
–
03606-0-002
Figure 70. Differential Input Architecture
The structure of the input SHA places certain requirements on
the input drive source. The differential input resistors are
typically 2 kΩ each. The combination of the pin capacitance,
CIN, and the hold capacitance, CH, is typically less than 5 pF. The
input source must be able to charge or discharge this capaci-
tance to 10-bit accuracy in one-half of a clock cycle. When the
SHA goes into sample mode, the input source must charge or
discharge capacitor CH from the voltage already stored on it to
the new voltage. In the worst case, a full-scale voltage step on
the input source must provide the charging current through the
RON of switch S1 (typically 100 Ω) to a settled voltage within
one-half of the ADC sample period. This situation corresponds
to driving a low input impedance. On the other hand, when the
source voltage equals the value previously stored on CH, the
hold capacitor requires no input current and the equivalent
input impedance is extremely high.
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