AD9146 Datasheet, PDF (22/52 Pages) Analog Devices – Dual, 16-Bit, 1230 MSPS, TxDAC+ Digital-to-Analog Converter

AD9146
Register
Name
Address
(Hex) Bits
Sync Control 0x10
7
6
3
[2:0]
0x11
[5:0]
Sync Status 0x12
7
6
0x13
[7:0]
Data
Receiver
Status
0x15
5
4
3
2
1
0
DCI Delay 0x16
2
[1:0]
Name
Sync enable
Data/FIFO rate toggle
Rising edge sync
Sync Averaging[2:0]
Sync Phase Request[5:0]
Sync lost
Sync locked
Sync Phase Readback[7:0]
LVDS FRAME level high
LVDS FRAME level low
LVDS DCI level high
LVDS DCI level low
LVDS data level high
LVDS data level low
Delay bypass
DCI Delay[1:0]
Description
1 = enable the synchronization logic.
0 = operate the synchronization at the FIFO reset rate.
1 = operate the synchronization at the data rate.
0 = sync is initiated on the falling edge of the sync input.
1 = sync is initiated on the rising edge of the sync input.
Sets the number of input samples that are averaged in
determining the sync phase.
000 = 1.
001 = 2.
010 = 4.
011 = 8.
100 = 16.
101 = 32.
110 = 64.
111 = 128.
This register sets the requested clock phase offset after sync.
The offset unit is in DACCLK cycles. This register enables
repositioning of the DAC output with respect to the sync
input. The offset can also be used to skew the DAC outputs
between the synchronized DACs.
000000 = 0 DACCLK cycles.
000001 = 1 DACCLK cycle.
…
111111 = 63 DACCLK cycles.
1 = synchronization was attained but has been lost.
1 = synchronization has been attained.
Indicates the averaged sync phase offset (6.2 format). If
this value differs from the Sync Phase Request[5:0] value
in Register 0x11, a sync timing error has occurred. For more
information, see the Sync Status Bits section.
00000000 = 0.0.
00000001 = 0.25.
…
11111110 = 63.50.
11111111 = 63.75.
One or both LVDS FRAME input signals have exceeded 1.7 V.
One or both LVDS FRAME input signals have crossed
below 0.7 V.
One or both LVDS DCI input signals have exceeded 1.7 V.
One or both LVDS DCI input signals have crossed below 0.7 V.
One or more LVDS Dx input signals have exceeded 1.7 V.
One or more LVDS Dx input signals have crossed below 0.7 V.
0 = enable the on-chip DCI delay feature. Set the delay
using Bits[1:0].
1 = bypass the on-chip DCI delay feature.
These bits control the delay applied to the DCI signal. The DCI
delay affects the sampling interval of the DCI with respect
to the Dx inputs. See Table 14.
00 = 105 ps delay of DCI signal.
01 = 375 ps delay of DCI signal.
10 = 615 ps delay of DCI signal.
11 = 720 ps delay of DCI signal.
Default
0
1
1
000
000000
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0
00
Rev. 0 | Page 22 of 52